1. Submicron Transferred-Substrate Heterojunction Bipolar Transistors M Rodwell, Y Betser,Q Lee, D Mensa, J Guthrie, S Jaganathan, T Mathew, P Krishnan, S Long University of California, Santa Barbara SC Martin, RP Smith, NASA Jet Propulsion Labs Supported by ONR (M Yoder, J Zolper, D Van Vechten), AFOSR ( H Schlossberg ) 24th International Conference on Infrared and Millimeter Waves

2. Why are HEMTs smaller & faster than HBTs ? FETs have deep submicron dimensions. 0.1 µm HEMTs with 400 GHz bandwidths (satellites). 5 million 1/4-µm MOSFETs on a 200 MHz, $500 CPU. FET lateral scaling decreases transit times. FET bandwidths then increase. HBTs have ~1 µm junctions. vertical scaling decreases electron transit times. vertical scaling increases RC charging times. lateral scaling should decrease RC charging times. HBT bandwidths should then increase. But, HBTs must first be modified...

3. Scaling for THz device bandwidths

5. Current-gain cutoff frequency in HBTs Collector velocities can be high: velocity overshoot in InGaAs Base bandgap grading reduces transit time substantially RC terms quite important for > 200 GHz ft devices

6. Excess Collector-Base Capacitance in Mesa HBTs base contacts: must be > 1 transfer length (0.3  m)  sets minimum collector width  sets minimum collector capacitance Ccb base resistance spreading resistance scales with emitter scaling contact resistance independent of emitter scaling  sets minimum base resistance  sets minimum R bb C cb time constant f max does not improve with submicron scaling

8. Transferred-Substrate HBTs: A Scalable HBT Technology Collector capacitance reduces with scaling: Bandwidth increases rapidly with scaling:

9. Thinning base, collector epitaxial layers improves ft, degrades fmax Lateral scaling provides moderate improvements in fmax Regrowth (similar to Si BJT !) should help considerably Transferred-substrate helps dramatically

10. Undercut-Collector Device for high f max Lucent Technologies (YK Chen) TRW Texas Instruments

13. 50 mm transferred-substrate HBT Wafer: Cu substrate

14. AlInAs/GaInAs graded base HBT Band diagram under normal operating voltages V ce = 0.9 V, V be = 0.7 V 400 Å 5E19 graded base (  E g = 2kT), 3000 Å collector Graded base Collector depletion region Emitter Schottky collector

15. Transferred-Substrate Heterojunction Bipolar Transistor Device with 0.6 µm emitter & 1.8 µm collector extrapolated fmax at instrument limits, >400 GHz

16. Why Mason’s Gain, U, is used to find f max : MAG/MSG can be above U MAG/MSG can be below U U is same for CE, CB, & CC U is not changed by pad parasitics U has -20 dB / decade slope to f max MSG slope is -10 dB / decade MAG has no fixed slope -for hybrid-  model comment: U is not given by: (CE, small C cbx ) ( CE, large C cbx )...above -20 dB/dec line …below -20 dB/dec line Plots generated using HP / EESOF simulator and standard hybrid-  model

17. DC-50 GHz & 75-110 GHz Network Analysis  waveguide-coupled micro-coax probes Parasitic probe-probe coupling S 12 error background: not corrected by calibration  gain measurements corrupted, worse for W-band Measuring High f max Transistors I corrupted W-band measurement

18. Offset reference planes, on-wafer LRL calibration standards separate probes to reduce coupling reference planes at transistor terminals Measuring High f max Transistors II 230  m

19. Line-reflect-line on-wafer cal. standards LoLo LoLo LoLo LoLo LoLo LoLo L o +L o L o +560  m+L o L o +1275  m+L o 20-60 GHz LINE 75-110 GHz LINE THROUGH LINE SHORT OPEN (reflect) DUT 75-110 GHz Calibration standards 20-60 GHz Calibration standards Calibration verification Device under test V= 2.04 x 10 8 m/s (  r = 2.7)

20. Submicron Transferred-Substrate HBT 20 dB / decade gain slope may NOT continue to 1 THz

21. Bandwidth vs Current Density

22. Bandwidth vs Vce Decrease in f   decreasing electron velocity with increased field

23. C cb Cancellation by Collector Space-Charge Collector space charge partially screens collector field. Increasing voltage decreases electron velocity,  modulates collector space-charge  offsets modulation of base charge  Ccb is reduced Moll & Camnitz 1992, Betser & Ritter 1999, Englemann & Liechti 1977 (MESFETs)

24. Measured Variation of Collector Transit Time with Bias f  data predicts 0.9 fF capacitance cancellation, 1 vs 6 mA

25. Capacitance cancellation: measured measured 0.64 fF decrease, 1  6 mA (vs 0.9 fF predicted) Expected Ccb reduction is observed in microwave Y 12

26. Device Model Element parameters are physically reasonable

27. Emitter Profile: Stepper Device 0.15  m e/b junction 0.5  m emitter stripe

28. Transferred-Substrate HBT: Stepper Lithography 0.4  m emitter, ~0.7  m collector

29. DC characteristics, stepper device We=0.2 X 6  m 2 Wc=1.5 X 9  m 2  =50

30. Given high fmax, vertical scaling exhanges reduced f max for increased f 

31. Transit times: HBT with 2kT base grading 2000 Å InGaAs collector 400 Å InGaAs base, 2kT bandgap grading

32. Gains: HBT with 2kA collector, 300 A base

33. Digital microwave / RF transmitters (DC-20 GHz) direct digital synthesis at microwave bandwidths microwave digital-analog converters Digital microwave / RF receivers delta-sigma ADCs with 10-30 GHz sample rates 16 effective bits at 100 MHz signal bandwidth ? Basic Science: 0.1 µm Ebeam device: 1000 GHz transistor (?) transistor electronics in the far-infrared Fast fiber optics, fast digital communications: 200 GHz f , 500 GHz f max device: ~ 75-90 Gb/s 160 Gb/s needs ~350 GHz f , 500 GHz f max Why would you want a 1 THz transistor ?

34. Transferred-Substrate HBT ICs: Key Features 100 GHz clock-rate ICs will need: very fast transistors short wires –> high IC density –> high thermal conductivity low capacitance wiring low ground inductance –> microstrip wiring environment Transferred Substrate HBT ICs offer: 800 GHz fmax now, > 1000 GHz with further scaling 250 GHz ft now, >300 GHz with improved emitter Ohmics copper substrates / thermal vias for heatsinking low capacitance (  = 2.5) wiring

35. THz-Bandwidth HBTs ??? 1) regrown P+++ InGaAs extrinsic base --> ultra-low-resistance 2) 0.05 µm wide emitter --> ultra low base spreading resistance 3) 0.05 µm wide collector --> ultra low collector capacitance 4) 100 Å, carbon-doped graded base --> 0.05 ps transit time 5) 1kÅ thick InP collector --> 0.1 ps transit time. Projected Performance: Transistor with 500 GHz ft, 1500 GHz fmax 1 2 3 4 5 deep submicron transferred-substrate regrown-base HBT

36. The wiring environment for 100 GHz logic

37. Why is Improved Wiring Essential? ground return loops create inductance Wire bond creates ground bounce between IC & package 30 GHz M/S D-FF in UCSB - mesa HBT technology Ground loops & wire bonds: degrade circuit & packaged IC performance

38. ADC digital sections input buffer ground return currents L ground  V in ground bounce noise Ground Bound Noise in ADCs Ground bounce noise must be ~100 dB below full-scale input Differential input will partly suppress ground noise coupling ~ 30 to 40 dB common-mode rejection feasible CMRR insufficient to obtain 100 dB SNR Eliminate ground bounce noise by good IC grounding

39. Microstrip IC wiring to Eliminate Ground Bounce Noise Transferred-substrate HBT process provides vias & ground plane.

40. Power Density in 100 GHz logic Transistors tightly packed to minimize delays 10 5 W/cm 2 HBT junction power density. ~10 3 W/cm 2 power density on-chip  75 C temperature rise in 500  m substrate. Solutions: Thin substrate to < 100  m Replace semiconductor with metal  copper substrate

41. Transferred-Substrate HBT Integrated Circuits 47 GHz master-slave flip-flop 7 dB, 5-80 GHz distributed amplifier 11 dB, 50+ GHz AGC / limiting amplifier 10 dB, 50+ GHz feedback amplifier

42. Transferred-Substrate HBT Integrated Circuits W-band VCO Clock recovery PLL multiplexer 2:1 demultiplexer (120 HBTs) 16 dB, DC-60 GHz amplifier 6.7 dB, DC-85 GHz amplifier

43. 6.7 dB, 85 GHz Mirror Darlington Amplifier 6.7 dB DC gain 3 dB bandwidth of 85 GHz f  -doubler (mirror Darlington) configuration

44. Frequency (GHz) dB S 21 S 11 S 22 18 dB, DC to > 50 GHz Darlington Amplifier Over 400 GHz Gain-BW, 2 transistors

46. Master-Slave Flip Flop: 100 GHz design target master, slave, clock buffer, output buffer: 76 HBTs

47. 33.0 GHz static divider output at 66.0 GHz input Measurement is setup-limited (source, bias tee, probe)

48. Fiber Optic ICs (not yet working !) AGC / limiting amplifier CML decision circuit PIN / transimpedance amplifier

49. Delta-Sigma ADC In Development (300 HBTs)

50. Transferred Substrate HBTs An ultrafast bipolar integrated circuit technology Ultrahigh fmax HBTs Low capacitance interconnects Superior heat sinking, low parasitic packaging Demonstrated: HBTs with 1 THz extrapolated fmax >66 GHz flip-flops, 85 GHz amplifiers,... Future: 0.1  m HBTs with fmax >> 1000 GHz (0.1  m, carbon) 100 GHz digital logic ICs --> DACs, DDS, ADCs, fiber