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CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 1 Scoreboarding  The following four steps replace ID, EX and WB steps  ID: Issue –

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Presentation on theme: "CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 1 Scoreboarding  The following four steps replace ID, EX and WB steps  ID: Issue –"— Presentation transcript:

1 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 1 Scoreboarding  The following four steps replace ID, EX and WB steps  ID: Issue – if a functional unit for instruction is free and no other active instruction has the same destination register (WAW) it can proceed, otherwise it stalls  ID: Read operands – a source operand is available if no earlier instruction is going to write it  EX: Execute – once the execution is complete this stage notifies the scoreboard  WB: Write results – scoreboard checks for WAR hazards and may stall write back

2 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 2 Scoreboarding  Operands are always read from register file – no advantage is taken of forwarding  This is no large penalty as write occurs immediately after the execution and not after MEM stage  Read operand and write result stages cannot overlap so we have 1 cycle latency

3 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 3 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status Integer YesLoadF6R2Yes Issue first load Time =1

4 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 4 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status Integer YesLoadF6R2Yes  First load reads operands Time =2 Second load cannot be issued due to structural hazard No

5 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 5 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status   YesLoadF6R2No Integer First load completes execution Time =3 Second load cannot be issued due to structural hazard

6 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 6 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status   First load writes the result and frees ALU  Time =4 YesLoadF6R2No Integer Second load cannot be issued due to structural hazard

7 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 7 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    YesLoadF2R3Yes Integer  Second load is issued Time =5

8 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 8 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes LoadF2R3Yes Integer    MultF0F2 F4 Integer No Yes Mult1 Second load reads operands Time =6 Mult is issued No

9 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 9 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes LoadF2R3No Integer    MultF0F2 F4 Integer No Yes Mult1   Sub is issued SubF8F6 F2 Integer Yes No Add Time =7 Second load completes execution Mult is stalled waiting for F2

10 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 10 Integer IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes    MultF0F2 F4 No Yes Mult1   Div is issued SubF8F6 F2 No Add  DivF10F0 F6 No Yes Mult1  Divide Time =8 Second load writes result Mult is stalled waiting for F2 Sub is stalled waiting for F2 YesLoadF2R3No Yes Integer

11 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 11 Yes IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes    MultF0F2 F4 No Mult1   SubF8F6 F2 No Add  DivF10F0 F6 No Yes Mult1    Divide Time =9 Mult reads operands Sub reads operands Div is stalled waiting for F0 Add cannot be issued due to structural hazard No

12 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 12 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes    MultF0F2 F4 No Mult1   Add cannot be issued due to structural hazard SubF8F6 F2 No Add  DivF10F0 F6 No Yes Mult1    Divide Time =10 Mult in execution (1 out of 10) Sub in execution (1 out of 2) Div is stalled waiting for F0 10

13 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 13 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes    MultF0F2 F4 No Mult1   SubF8F6 F2 No Add  DivF10F0 F6 No Yes Mult1     Divide Time =11 Add cannot be issued due to structural hazard Mult in execution (2 out of 10) Sub completes execution Div is stalled waiting for F0 10

14 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 14 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes    MultF0F2 F4 No Mult1    DivF10F0 F6 No Yes Mult1     Divide Time =12 Mult in execution (3 out of 10) Sub writes result, frees adder Div is stalled waiting for F0 Add cannot be issued due to structural hazard 10 Yes SubF8F6 F2 No Add

15 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 15 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes    MultF0F2 F4 No Mult1   Add is issued Yes Add  DivF10F0 F6 No Yes Mult1      AddF6F8 F2 Divide Time =13 10 Mult in execution (4 out of 10) Div is stalled waiting for F0

16 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 16 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes    MultF0F2 F4 No Mult1   Add reads operands Yes Add  DivF10F0 F6 No Yes Mult1      AddF6F8 F2  Divide Time =14 Mult in execution (5 out of 10) Div is stalled waiting for F0 10 No

17 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 17 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes    MultF0F2 F4 No Mult1   Add in execution (1 out of 2) No Add  DivF10F0 F6 No Yes Mult1      AddF6F8 F2  Divide Time =15 10 Mult in execution (6 out of 10) Div is stalled waiting for F0 15

18 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 18 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes    MultF0F2 F4 No Mult1   No Add  DivF10F0 F6 No Yes Mult1      AddF6F8 F2   Divide Time =16 Add completes execution Mult in execution (7 out of 10) Div is stalled waiting for F0 10 15

19 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 19 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes    MultF0F2 F4 No Mult1   No Add  DivF10F0 F6 No Yes Mult1      AddF6F8 F2   Divide Time =17 Add is stalled, WAR hazard Mult in execution (8 out of 10) Div is stalled waiting for F0

20 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 20 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes    MultF0F2 F4 No Mult1   No Add  DivF10F0 F6 No Yes Mult1      AddF6F8 F2    Divide Time =19 Add is stalled, WAR hazard Mult completes execution Div is stalled waiting for F0

21 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 21 No IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes    Add   No  DivF10F0 F6 Yes      AddF6F8 F2    Time =20 Add is stalled, WAR hazard Mult writes result Div is stalled waiting for F0 YesMultF0F2 F4 No Mult1 Divide

22 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 22 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes    Add   No  DivF10F0 F6 Yes      AddF6F8 F2     Divide Time =21 No Div reads operands Add is stalled, WAR hazard

23 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 23 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes      Add writes result  DivF10F0 F6 No          Divide  Time =22 Div in execution (1 out of 40) 22 Yes Add No AddF6F8 F2

24 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 24 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status    Yes      Div completes execution  DivF10F0 F6 No          Divide   Time =61

25 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 25 IssueRead operandsExecution complete Write result L.D F6, 34(R2) L.D F2, 45(R3) MUL.D F0, F2, F4 SUB.D F8, F6, F2 DIV.D F10, F0, F6 ADD.D F6, F8, F2  Instruction status BusyOp F i F j F k Q j Q k R j R k Integer ALU FP Mult1 FP Mult2 FP Add FP Div Functional unit status F 0 … F 2 … F 4 … F 6 … F 8 … F 10 … F 12 Functional unit Register result status         Div writes result              Time =62 Yes DivF10F0 F6 No Divide

26 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 26 Tomasulo’s Algorithm  Use reservation stations that will hold operands for instructions waiting to issue  Reservation station fetches the operand as soon as it is available  Pending instructions read operands from reservation stations  When writes overlap in execution, only the last write actually updates the register

27 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 27 Tomasulo’s Algorithm FP registers Instruction queue Address unit Memory unit FP adders FP multipliers 43214321 43214321 From instruction unit Reservation stations Store buffers Load buffers Data Address Common data bus LOAD-STORE OPERATIONS FP OPERATIONS

28 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 28 Tomasulo’s Algorithm  Each reservation station holds the opcode for the pending instruction and either operand values or names of reservation stations that will provide them  Load and store buffers hold data and addresses for memory access  Transfer of all data goes over the common data bus

29 CIS 662 – Computer Architecture – Fall 2004 - Class 11 – 10/12/04 29 Homework ● Due Tuesday, October 19 by the end of the class ● Submit either in class (paper) or by E-mail (PS or PDF only) or bring the paper copy to my office ● Show scheduling of the following code using scoreboard (assume one integer ALU, two FP multipliers, one FP adder and one FP divider) LD F2, 0(R2) LD F4, 100(R3) ADD F8, F2, F2 MUL F6, F4, F8 SUB F6, F2, F4

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