1. AMC40 firmware Data format discussions 17/10/2013Guillaume Vouters1

2. Error Recovering Data Processing LLT decision MEP building BCID Alignment Decoding Memory DDR3 Computer Network CCPC resets ECS ODIN 40 SOL 40 Throttle Memory (FE data) FE data CLK x6 Low Level Interface If 80 bits width GBT If 112bits width GBT Throttle CCPC 1. Mini DAQ architecture Guillaume Vouters 17/10/20132

3. 3Guillaume Vouters Header 100 Data 100 Header 101 Data 101 Header 102 Data 102 Header 103 Data 103 Data 104 Header 104 Data 103 Frame width = GBT time Bx0 Bx1 Bx2 Bx3 Bx4 Bit 0Bit 80 or 112 Header 100 Data 100 100 FIFO Bit 0MSB Header 101 Data 101 Header 103 Data 103 103 Header 104 Data 104 Header 102 Data 102 GBT frame 112 or 80 bits MUX  …  Number of bits of the FIFO width 17/10/2013 Bit 1 Bit 2 Data Format

4. 4Guillaume Vouters Old data format (fixed length header !) New data format (variable length header !) Electronics Architecture of the LHCb Upgrade : http://cds.cern.ch/record/1340939?ln=enhttp://cds.cern.ch/record/1340939?ln=en This is the data encoding/decoding guidelines, sub-detectors specific coding must also be supported. 17/10/2013 Data Format

5. 5Guillaume Vouters17/10/2013

6. Compilation 6Guillaume Vouters New data format VS GBT width VS Number of Inputs inputs Old data format VS GBT width VS Number of Inputs data length unit value = 4 17/10/2013 inputs

7. UT Compilation estimation 7Guillaume Vouters17/10/2013

8. Compilation 8Guillaume Vouters If data_length(8bit) in the header = 0x0A If data length unit value = 1 : real data length = 10bits If data length unit value = 4 : real data length = 40bits If data length unit value = 8 : real data length = 80bits Data length unit value GBT frame 112 or 80 bits MUX  …  Number of bits of the FIFO width Bit 0 Bit 8 Bit 112 or 80 Bit 4 Data length unit value = 4 This completely true with a fixed length header and part true for variable length header Even less true for UT with very flexible header 17/10/2013

9. Compilation 9Guillaume Vouters If data_length(8bit) in the header = 0x0A If data length unit value = 1 : real data length = 10bits If data length unit value = 4 : real data length = 40bits If data length unit value = 8 : real data length = 80bits Data length unit value Test done with variable length header (new data format) The data length unit value shoud be bigger or equal to 4. We should forbid smaller than 4. 17/10/2013

10. UT AMC40 firmware 10Guillaume Vouters17/10/2013 Decoding BCID Alignment 72 for UT 24 for others MEP building Data Processing

11. 4. e-links number 11Guillaume Vouters17/10/2013 3 e-links ? e-links 13151 23954

12. 4. Compilation 12Guillaume Vouters Summary Compilation Because of the data format we have, the resources taken by the decoding block and the BCID alignment will be substantial The 2 options are : - Buy a bigger FPGA - Reduce the firmware as much as possible Buy a bigger FPGA  More expensive  Very complicated to power ! The current one on the AMC40 is already tricky to power. See Jean Pierre Cachemiche’s talk at TWEPP https://indico.cern.ch/contributionDisplay.py?contribId=244&confId=228972 https://indico.cern.ch/contributionDisplay.py?contribId=244&confId=228972 Reduce the firmware as much as possible  There are some ways to try to reduce the current resources (but nothing magical ! Do not expect a drastically reduction of the resources)  At some point maybe we will need to take some decision such as having a less complicated header or using only the 80 bits GBT frame for example… 17/10/2013

13. importa 4. Compilation 13Guillaume Vouters X axis : Nb of channels of 8 bits + Number of bits for the BCID + rest of the header (info + data length) Federico Alessio’s compilation graphs of FE data generator Y axis : LC combinational Last point very important for FE sub detectors: What we are experienced with the decoding, FE may experience the same problems also for the encoding. FE data format decisions have impacts on decoding/encoding and resources. More information tomorrow in Federico’s talk at the LHCb upgrade electronics meeting : https://indico.cern.ch/conferenceDisplay.py?confId=225753 https://indico.cern.ch/conferenceDisplay.py?confId=225753 This is for 1 FPGA or 1 ASIC dealing with 1 GBT 17/10/2013