1. ELEC 2200-002 Digital Logic Circuits Fall 2015 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu Fall 2015, Nov 30 ELEC2200-002 Lecture 8 1

2. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 2 Power and Delay of a Transition V DD Ground CLCL R on R = large v i (t) v o (t) i c (t) C L =Total load capacitance for gate; includes transistor capacitances of driving gate + routing capacitance + transistor capacitances of driven gates; obtained by layout analysis.

3. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 3 Charging of a Capacitor V DD C = C L R = R on i(t) i(t) v(t) Charge on capacitor, q(t)=C v(t) Current, i(t)=dq(t)/dt=C dv(t)/dt t = 0

4. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 4 i(t)=C dv(t)/dt=[V DD – v(t)] /R dv(t) dt ∫ ───── = ∫ ──── V DD – v(t) RC – t ln [V DD – v(t)]=──+ A RC Initial condition, t = 0, v(t) = 0 → A = ln V DD – t v(t) =V DD [1 – exp(───)] = 0.5V DD RC t = 0.69 RC

5. Delay: Definitions Rise time is the time a signal takes to rise from 10% to 90% of its peak value. Fall time is the time a signal takes to drop from 90% to 10% of its peak value. Delay of a gate or circuit is the time interval between the input crossing 50% of peak value and the output crossing 50% of peak value. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 5 1→0 0→1 NOT gate A B VDD GND Fall timeA Time 10% VDD 90% VDD VDD GND Rise timeB Time 10% VDD 90% VDD Gate delay

6. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 6 Inverter: Idealized Input t = 0 V DD 0.5V DD GND V DD GND time 0.69CR INPUT OUTPUT Gate delay

7. Timing of a Digital Circuit Most digital circuits are clocked synchronous finite state machines (FSM). Fall 2015, Nov 30 ELEC2200-002 Lecture 8 7 FF Primary Inputs Primary Outputs Combinational circuit (Gates interconnected without feedback) Clock

8. Large Circuit Timing Analysis Determine gate delays: From layout analysis, or use approximate delays: –Gate delay increases in proportion to number of fanouts (increased capacitance) –Delay decreases in proportion to increase in gate size (reduced transistor channel resistance) Purpose of analysis is to verify timing behavior – determine maximum speed of operation. Methods of analysis: Circuit simulation – most accurate, expensive (Spice program) Static timing analysis (STA) – most efficient, approximate Fall 2015, Nov 30 ELEC2200-002 Lecture 8 8

9. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 9 Static Timing Analysis (STA) Combinational logic for critical path delays. Circuit represented as an acyclic directed graph (DAG). Gates characterized by delays; gate function ignored. No inputs are used – worst-case analysis – static analysis (simulation would be dynamic).

10. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 10 Combinational Circuit of an FSM A1A1 B1B1 D1D1 E4E4 F2F2 J1J1 G 1 H1H1 C2C2 Gate delay Input to Output delay must not exceed clock period Fanout = 4

11. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 11 Static Timing Analysis (STA) Step 1 A1A1 B1B1 D1D1 E4E4 F2F2 J1J1 G 1 H1H1 C2C2 Levelize circuit. Initialize arrival times at primary inputs to 0. 0000 0000 0000 0000 Level 0 1 2 3 4 5 Level of a gate is one greater than the maximum of fanin gate levels

12. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 12 Static Timing Analysis (STA) Step 2 A1A1 B1B1 D1D1 E4E4 F2F2 J1J1 G 1 H1H1 C2C2 0000 0000 0000 0000 Level 0 1 2 3 4 5 Determine output arrival times of gates in level order. 1 1 2 1 6 8 9 10 9 Arrival time at a gate output = maximum of input arrivals + gate delay

13. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 13 Static Timing Analysis (STA) Step 3 A1A1 B1B1 D1D1 E4E4 F2F2 J1J1 G 1 H1H1 C2C2 0000 0000 0000 0000 Level 0 1 2 3 4 5 1 1 2 1 6 8 9 10 9 Trace critical paths from the output with longest arrival time. Critical path: C, E, F, G, H; delay = 10

14. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 14 Power in CMOS Logic (Inverter) F. M. Wanlass and C. T. Sah, “Nanowatt Logic using Field-Effect Metal-Oxide-Semiconductor Triodes,” IEEE International Solid- State Circuits Conference Digest, vol. IV, February 1963, pp. 32-33. No current flows from power supply! Where is power consumed? VDD GND

15. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 15 Three Components of Power Dynamic, when output changes –Signal transitions (major component) Logic activity Glitches –Short-circuit (small, often neglected) Static, when signal is in steady state –Leakage (small) P total =P dyn + P stat =P tran + P sc + P stat

16. Charging of Output Capacitor From Slide 4: Fall 2015, Nov 30 ELEC2200-002 Lecture 8 16 – t v(t)=V [1 – exp( ── )] RC dv(t) V – t i(t)=C ───=── exp( ── ) dt R RC

17. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 17 Total Energy Per Charging Transition from Power Supply ∞∞ V 2 – t E trans =∫ V i(t) dt=∫ ── exp( ── ) dt 00 R RC =CV 2

18. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 18 Energy Dissipated Per Transition in Transistor Channel Resistance ∞ V 2 ∞ -2t R ∫ i 2 (t) dt=R ── ∫ exp( ── ) dt 0 R 2 0 RC 1 = ─ CV 2 2

19. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 19 Energy Stored in Charged Capacitor ∞∞ - t V - t ∫ v(t) i(t) dt = ∫ V [1-exp( ── )] ─ exp( ── ) dt 00 RC R RC 1 = ─ CV 2 2

20. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 20 Transition Power Gate output rising transition – –Energy dissipated in pMOS transistor = ½CV 2 – –Energy stored in capacitor = ½CV 2 Gate output falling transition – –Energy dissipated in nMOS transistor = ½ CV 2 Energy dissipated per transition = ½ CV 2 Power dissipation: P trans =E trans α f ck = ½ α f ck CV 2 α = activity factor = prob.(gate has transition) f ck = clock frequency

21. Power Density of a Chip Assume dynamic power is major component. Power density = ½ α f ck CV 2 × gate density C = average gate capacitance Gate density = number of gates per unit area Example: α = 0.5, f ck = 1GHz, C = 1pF, V = 1 volt, gate density = 1 million gates/cm 2 Power density = 250 watts/cm 2 Fall 2015, Nov 30 ELEC2200-002 Lecture 8 21

22. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 22 CMOS Gate Power V Ground C R = R on Large resistance v i (t) v(t) i(t) time v(t) i(t) i sc (t) Leakage current i sc (t) Output signal transition Dynamic current Short-circuit current Leakage current

23. Fall 2015, Nov 30 ELEC2200-002 Lecture 8 23 References Delay modeling, simulation and testing: – –M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000. Timing analysis and design: – –G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994. – –N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999. PrimeTime (A static timing analysis tool): – –H. Bhatnagar, Advanced ASIC Chip Synthesis, Second Edition, Springer, 2002 CMOS digital circuit power: – –A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS Design, Boston: Springer, 1995.