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CS-EE 481 Spring 2006 1Founder’s Day, 2006 University of Portland School of Engineering CMOS Digital Lock Authors Julie Barton-Smith Cory Johnson Jessica.

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Presentation on theme: "CS-EE 481 Spring 2006 1Founder’s Day, 2006 University of Portland School of Engineering CMOS Digital Lock Authors Julie Barton-Smith Cory Johnson Jessica."— Presentation transcript:

1 CS-EE 481 Spring 2006 1Founder’s Day, 2006 University of Portland School of Engineering CMOS Digital Lock Authors Julie Barton-Smith Cory Johnson Jessica Rice Advisor Dr. Inan, Dr. Osterberg Industry Representative Mr. Wes Mickanin Compound Semiconductor Consulting

2 CS-EE 481 Spring 2006 2Founder’s Day, 2006 University of Portland School of Engineering Agenda Introduction Julie Barton-Smith Background Julie Barton-Smith Methods Cory Johnson Results Cory Johnson Conclusions Jessica Rice Demonstration Jessica Rice

3 CS-EE 481 Spring 2006 3Founder’s Day, 2006 University of Portland School of Engineering Introduction Additional Recognition –MOSIS –Dr. Lu –Dr. Hoffbeck Design & Implement Keypad Lock Mainstream Technology

4 CS-EE 481 Spring 2006 4Founder’s Day, 2006 University of Portland School of Engineering Background CMOS Chip = Computer Chip Unlock door given correct code After 3 tries alarm sounds Key Override

5 CS-EE 481 Spring 2006 5Founder’s Day, 2006 University of Portland School of Engineering Methods Designed & Tested Logic Layout Circuit Sent Layout to be Fabricated Made Contingency Model Designed Interfaces Tested & Debugged

6 CS-EE 481 Spring 2006 6Founder’s Day, 2006 University of Portland School of Engineering Results Block Diagram

7 CS-EE 481 Spring 2006 7Founder’s Day, 2006 University of Portland School of Engineering Conclusions CMOS Digital Lock MOSIS Grant Possible Features –Noise when buttons pushed –Battery / Wall Power

8 CS-EE 481 Spring 2006 8Founder’s Day, 2006 University of Portland School of Engineering Demonstration Code: ABCD Light: Red = Lock, Green = Unlocked Alarm

9 CS-EE 481 Spring 2006 9Founder’s Day, 2006 University of Portland School of Engineering Circuit Layout


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