Presentation is loading. Please wait.

Presentation is loading. Please wait.

Penn ESE370 Fall2013 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 20, 2013 MOS Transistor.

Similar presentations


Presentation on theme: "Penn ESE370 Fall2013 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 20, 2013 MOS Transistor."— Presentation transcript:

1 Penn ESE370 Fall2013 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 20, 2013 MOS Transistor Operating Regions Part 1

2 Today MOS Transistor Topology Threshold Operating Regions –Resistive –Saturation –Velocity Saturation –Subthreshold Penn ESE370 Fall2013 -- DeHon 2

3 Last Time Penn ESE370 Fall2013 -- DeHon 3

4 Depletion region  excess carriers depleted Penn ESE370 Fall2013 -- DeHon 4 Refinement

5 Body Contact Fourth terminal Also effects fields Usually common across transistors Penn ESE370 Fall2013 -- DeHon 5

6 No Field V GS =0, V DS =0 Penn ESE370 Fall2013 -- DeHon 6

7 Apply V GS >0 Accumulate negative charge –Repel holes (fill holes) Penn ESE370 Fall2013 -- DeHon 7 + + + + - - - - - - - - -

8 Channel Evolution Increasing Vgs Penn ESE370 Fall2013 -- DeHon 8

9 Gate Capacitance Penn ESE370 Fall2013 -- DeHon 9 Changes based on operating region.

10 Inversion Surface builds electrons –Inverts to n-type –Draws electrons from n + source Penn ESE370 Fall2013 -- DeHon 10

11 Threshold Voltage where strong inversion occurs  threshold voltage –Around 2 ϕ F –Engineer by controlling doping (N A ) Penn ESE370 Fall2013 -- DeHon 11

12 Resistive Region V GS >V T, V DS small Penn ESE370 Fall2013 -- DeHon 12

13 Resistive Region V GS >V T, V DS small V GS fixed  looks like resistor –Current linear in V DS Penn ESE370 Fall2013 -- DeHon 13

14 Linear (Resistive) Region Penn ESE370 Fall2013 -- DeHon 14

15 Penn ESE370 Fall2013 -- DeHon 15 Blue curve marks transition from Linear to Saturation Linear (Resistive) Region

16 Penn ESE370 Fall2013 -- DeHon 16 Dimensions Channel Length (L) Channel Width (W) Oxide Thickness (T ox )

17 Preclass Ids for identical transistors in parallel? Penn ESE370 Fall2013 -- DeHon 17

18 Preclass Ids for identical transistors in series? –(Vds small) Penn ESE370 Fall2013 -- DeHon 18

19 Transistor Strength (W/L) Penn ESE370 Fall2013 -- DeHon 19 S D

20 Transistor Strength (W/L) Shape dependence match Resistance intuition –Wider = parallel resistors  decrease R –Longer = series resistors  increase R Penn ESE370 Fall2013 -- DeHon 20 S D

21 L drawn vs. L effective Doping not perfectly straight Spreads under gate Effective L smaller than draw gate width Penn ESE370 Fall2013 -- DeHon 21

22 Channel Voltage Voltage varies along channel Think of channel as resistor Penn ESE370 Fall2013 -- DeHon 22

23 Preclass 2 What is voltage in the middle of a resistive medium? –(halfway between terminals) Penn ESE370 Fall2013 -- DeHon 23

24 Voltage in Channel Think of channel as resistive medium –Length = L –Area = Width * Depth(inversion) What is voltage in the middle of the channel? –L/2 from S and D ? Penn ESE370 Fall2013 -- DeHon 24

25 Channel Voltage Voltage varies along channel If think of channel as resistor –Serves as a voltage divider between V S and V D Penn ESE370 Fall2013 -- DeHon 25

26 Impact on Inversion What happens when –Vgs=2Vth ? –Vds=2Vth? What is Vmiddle-Vs? Penn ESE370 Fall2013 -- DeHon 26

27 Channel Field When voltage gap V G -V x drops below V TH, drops out of inversion –Occurs when: V GS -V DS < V TH –What does this mean about conduction? Penn ESE370 Fall2013 -- DeHon 27

28 Preclass 3 What is Vm? Penn ESE370 Fall2013 -- DeHon 28

29 Channel Field When voltage gap V G -V x drops below V T, drops out of inversion –Occurs when: V GS -V DS < V T –What is voltage at Vmiddle if conduction stops? –What does that mean about conduction? Penn ESE370 Fall2013 -- DeHon 29

30 Contradiction? Vg-Vx < Vt  cutoff (no current) No current  Vg-Vx=Vgs Vg-Vx=Vgs > Vt  current flows Penn ESE370 Fall2013 -- DeHon 30

31 Way out? Vg-Vx < Vt  cutoff (no current) No current  Vg-Vx=Vgs Vg-Vx=Vgs > Vt  current flows Penn ESE370 Fall2013 -- DeHon 31 Act like Vds at Vgs-Vt

32 Channel Field When voltage gap V G -V x drops below V T, drops out of inversion –Occurs when: V GS -V DS < V T –Channel is “pinched off” Penn ESE370 Fall2013 -- DeHon 32

33 Channel Field When voltage gap V G -V x drops below V T, drops out of inversion –Occurs when: V GS -V DS < V T –Channel is “pinched off” –Current will flow, but cannot increase any further Penn ESE370 Fall2013 -- DeHon 33

34 Pinch Off When voltage drops below V T, drops out of inversion –Occurs when: V GS -V DS < V T Conclusion: –current cannot increase with V DS once V DS > V GS -V T Penn ESE370 Fall2013 -- DeHon 34

35 Saturation In saturation, V DS-effective =V x = V GS -V T Becomes: Penn ESE370 Fall2013 -- DeHon 35

36 Saturation V DS > V GS -V T Penn ESE370 Fall2013 -- DeHon 36

37 Penn ESE370 Fall2013 -- DeHon 37 Blue curve marks transition from Linear to Saturation Saturation Region

38 Class Ended Here Penn ESE370 Fall2013 -- DeHon 38

39 Switching Operation Consider Inverter Start with in=0V Output voltage? What does first-order model say about NFET? Penn ESE370 Fall2013 -- DeHon 39

40 Switching Operation Input rises from 0V When cross into new region? What region cross into? Ids Current? What happens to Ids as V continues to rise? What is happening to Vout? Penn ESE370 Fall2013 -- DeHon 40

41 Switching Operation Input at Vdd When NFET change operating regions? Which region move into? What’s happening to Vout? What region when settles to static voltage? Penn ESE370 Fall2013 -- DeHon 41

42 Penn ESE370 Fall2013 -- DeHon 42 Retrace Transition

43 Approach Identify Region Drives governing equations Use to understand operation Penn ESE370 Fall2013 -- DeHon 43

44 Big Idea 3 Regions of operation for MOSFET –Subthreshold –Resistive –Saturation Penn ESE370 Fall2013 -- DeHon 44

45 Admin Text 3.3.2 – highly recommend read –Second half on Friday HW4 out –Get started over weekend Penn ESE370 Fall2013 -- DeHon 45


Download ppt "Penn ESE370 Fall2013 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 20, 2013 MOS Transistor."

Similar presentations


Ads by Google