1. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 LECTURE : KEEE 4425 WEEK 3/2 STATIC CHARACTERISTICS OF THE CMOS INVERTERS

2. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005

3. Review: Design Abstraction Levels SYSTEM GATE CIRCUIT V out V in CIRCUIT V out V in MODULE + DEVICE n+ SD G

4. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Review: The MOS Transistor Gate oxide n+ SourceDrain p substrate Bulk (Body) p+ stopper Field-Oxide (SiO 2 ) n+ Polysilicon Gate L W

5. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Switch Model of PMOS Transistor Gate Source (of carriers) Drain (of carriers) | V GS | | V GS | > | V DD – | V T | || V GS | < | V DD – |V T | | Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’) R on

6. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Switch Model of NMOS Transistor Gate Source (of carriers) Drain (of carriers) | V GS | | V GS | < | V T | | V GS | > | V T | Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’) R on

7. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 CMOS Inverter Load Lines I Dn (A) V out (V) X 10 -4 V in = 1.0V V in = 1.5V V in = 2.0V V in = 2.5V 0.25um, W/L n = 1.5, W/L p = 4.5, V DD = 2.5V, V Tn = 0.4V, V Tp = -0.4V V in = 0V V in = 0.5V V in = 1.0V V in = 1.5V V in = 0.5V V in = 2.0V V in = 2.5V V in = 2V V in = 1.5V V in = 1V V in = 0.5V V in = 0V PMOSNMOS

8. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 CMOS Inverter: V DD V out CLCL V in

9. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 CMOS Inverter: Steady State Response V DD RnRn V out = 0 V in = V DD V DD RpRp V out = 1 V in = 0 V OL = 0 V OH = V DD V M = f(R n, R p )

10. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 CMOS Properties Full rail-to-rail swing  high noise margins –Logic levels not dependent upon the relative device sizes  transistors can be minimum size  ratioless Always a path to V dd or GND in steady state  low output impedance (output resistance in k  range)  large fan-out (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator)  nearly zero steady-state input current No direct path steady-state between power and ground  no static power dissipation Propagation delay function of load capacitance and resistance of transistors

11. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Review: Short Channel I-V Plot (NMOS) I D (A) V DS (V) X 10 -4 V GS = 1.0V V GS = 1.5V V GS = 2.0V V GS = 2.5V Linear dependence NMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = 0.4V

12. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Review: Short Channel I-V Plot (PMOS) I D (A) V DS (V) X 10 -4 V GS = -1.0V V GS = -1.5V V GS = -2.0V V GS = -2.5V PMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = -0.4V l All polarities of all voltages and currents are reversed

13. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Transforming PMOS I-V Lines I DSp = -I DSn V GSn = V in ; V GSp = V in - V DD V DSn = V out ; V DSp = V out - V DD V out I Dn V GSp = -2.5 V GSp = -1 Mirror around x-axis V in = V DD + V GSp I Dn = -I Dp V in = 1.5 V in = 0 V in = 1.5 V in = 0 Horiz. shift over V DD V out = V DD + V DSp l Want common coordinate set V in, V out, and I Dn

14. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 CMOS Inverter: Switch Model of Dynamic Behavior V DD RnRn V out CLCL V in = V DD V DD RpRp V out CLCL V in = 0 l Gate response time is determined by the time to charge C L through R p (discharge C L through R n ) response determined mainly by the output capacitance of the gate, CL - drain diffusion capacitance of the NMOS and PMOS transistors; the connecting wires, and the input capacitances of the fan-out gates A fast gate is built either by keeping the output capacitance small or by decreasing the on-resistance or the transistor (or both) Decreasing the on-resistance achieved by increasing the W/L ratio of the device Be award that the on-resistance of the NMOS and PMOS transistors is not constant; rather it is a nonlinear function of the voltage across the transistor

15. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 CMOS Inverter VTC V in (V) V out (V) NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off

16. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 CMOS Inverter Load Lines I Dn (A) V out (V) X 10 -4 V in = 1.0V V in = 1.5V V in = 2.0V V in = 2.5V 0.25um, W/L n = 1.5, W/L p = 4.5, V DD = 2.5V, V Tn = 0.4V, V Tp = -0.4V V in = 0V V in = 0.5V V in = 1.0V V in = 1.5V V in = 0.5V V in = 2.0V V in = 2.5V V in = 2V V in = 1.5V V in = 1V V in = 0.5V V in = 0V PMOSNMOS Note all operating points are located either at the high or low output levels

17. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 CMOS Inverter VTC V out (V) V in (V) NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off VTC of the inverter exhibits a very narrow transition zone; high gain during switching transient (when both PMOS and NMOS are simultaneously on and in saturation). In that region, a small change in input voltage results in a large output voltage variation. Indicate on VTC plot where VTn and VTp lie

18. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Threshold Voltage Concept S D p substrate B G V GS + - n+ depletion region n channel The value of V GS where strong inversion occurs is called the threshold voltage, V T

19. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 The Threshold Voltage where V T0 is the threshold voltage at V SB = 0 and is mostly a function of the manufacturing process –Difference in work-function between gate and substrate material, oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc. V SB is the source-bulk voltage  F = -  T ln(N A /n i ) is the Fermi potential (  T = kT/q = 26mV at 300K is the thermal voltage; N A is the acceptor ion concentration; n i  1.5x10 10 cm -3 at 300K is the intrinsic carrier concentration in pure silicon)  =  (2q  si N A )/C ox is the body-effect coefficient (impact of changes in V SB ) (  si =1.053x10 -10 F/m is the permittivity of silicon; C ox =  ox /t ox is the gate oxide capacitance with  ox =3.5x10 -11 F/m) V T = V T0 +  (  |-2  F + V SB | -  |-2  F |)

20. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 The Body Effect V BS (V) V T (V) l V SB is the substrate bias voltage (normally positive for n-channel devices with the body tied to ground) l A negative bias causes V T to increase from 0.45V to 0.85V

21. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Transistor in Linear Mode S D B G n+ Assuming V GS > V T V GS V DS IDID x V(x) -+ The current is a linear function of both V GS and V DS

22. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Voltage-Current Relation: Linear Mode For long-channel devices (L > 0.25 micron) When V DS  V GS – V T I D = k’ n W/L [(V GS – V T )V DS – V DS 2 /2] where k’ n =  n C ox =  n  ox /t ox = is the process transconductance parameter (  n is the carrier mobility (m 2 /Vsec)) k n = k’ n W/L is the gain factor of the device For small V DS, there is a linear dependence between V DS and I D, hence the name resistive or linear region

23. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Transistor in Saturation Mode V DS > V GS - V T S D B G V GS IDID V GS - V T -+ n+ Pinch- off Assuming V GS > V T V DS The current remains constant (saturates). As VDS is increased, the assumption that the channel voltage is larger than the threshold all along the channel ceases to hold when VGS – V(x) < VT At this point, the induced charge is zero and the conducting channel disappears or is pinched off. No channel exists in the vicinity of the drain region (VGS - VDS <= VT) The voltage difference over the induced channel remains fixed (at VGS -VT) and the current remains constant (or saturates)

24. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Voltage-Current Relation: Saturation Mode For long channel devices When V DS  V GS – V T I D ’ = k’ n /2 W/L [(V GS – V T ) 2 ] since the voltage difference over the induced channel (from the pinch-off point to the source) remains fixed at V GS – V T However, the effective length of the conductive channel is modulated by the applied V DS, so I D = I D ’ (1 + V DS ) where is the channel-length modulation (varies with the inverse of the channel length)

25. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 The Body Effect V BS (V) V T (V) l V SB is the substrate bias voltage (normally positive for n-channel devices with the body tied to ground) l A negative bias causes V T to increase from 0.45V to 0.85V

26. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Current Determinates For a fixed V DS and V GS (> V T ), I DS is a function of –the distance between the source and drain – L –the channel width – W –the threshold voltage – V T –the thickness of the SiO 2 – t ox –the dielectric of the gate insulator (SiO 2 ) –  ox –the carrier mobility for nfets:  n = 500 cm 2 /V-sec for pfets:  p = 180 cm 2 /V-sec

27. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Relative Transistor Sizing When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to –maximize the noise margins and –obtain symmetrical characteristics

28. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Switching Threshold = V M where V in = V out (both PMOS and NMOS in saturation since V DS = V GS ) V M  rV DD /(1 + r) where r = k p V DSATp /k n V DSATn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Want V M = V DD /2 (to have comparable high and low noise margins), so want r  1 (W/L) p = k n ’V DSATn (V M -V Tn -V DSATn /2) (W/L) n k p ’V DSATp (V DD -V M +V Tp +V DSATp /2)

29. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Switch Threshold Example V T0 (V)  (V 0.5 ) V DSAT (V ) k’(A/V 2 ) (V -1 ) NMOS0.430.40.63115 x 10 -6 0.06 PMOS-0.4 -30 x 10 -6 -0.1 (W/L) p 115 x 10 -6 0.63 (1.25 – 0.43 – 0.63/2) (W/L) n -30 x 10 -6 -1.0 (1.25 – 0.4 – 1.0/2) =xx = 3.5 (W/L) p = 3.5 x 1.5 = 5.25 for a V M of 1.25V In our generic 0.25 micron CMOS process, using the process parameters from J. Rabaey et al, a V DD = 2.5V, and a minimum size NMOS device ((W/L) n of 1.5)

30. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Simulated Inverter V M (W/L) p /(W/L) n V M (V)  V M is relatively insensitive to variations in device ratio setting the ratio to 3, 2.5 and 2 gives V M ’s of 1.22V, 1.18V, and 1.13V  Increasing the width of the PMOS moves V M towards V DD  Increasing the width of the NMOS moves V M toward GND.1 Note: x-axis is semilog ~3.4

31. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Noise Margins Determining V IH and V IL V in V out V OH = V DD VMVM By definition, V IH and V IL are where dV out /dV in = -1 (= gain) V OL = GND A piece-wise linear approximation of VTC NM H = V DD - V IH NM L = V IL - GND Approximating: V IH = V M - V M /g V IL = V M + (V DD - V M )/g So high gain in the transition region is very desirable

32. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Noise Margins Noise- unwanted variations in voltages or currents. In digital cct, if the magnitude of the noise at a logic node is too large, logic errors can be introduced into into the system. However, if the noise amplitude is less than a specified value, called the noise margin, the noise signal will be attenuated as it passes through a logic gate or cct, while the logic signals will be transmitted without error A high gain in the transition region is VERY desirable. In the extreme case of an infinite gain, the noise margins simplify to VOH – VM and VM – VOL for NMH (ideally, VDD – VM) and NML (ideally, VM – GND), respectively, and span the complete voltage swing.

33. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 CMOS Inverter VTC from Simulation V in (V) V out (V) 0.25um, (W/L) p /(W/L) n = 3.4 (W/L) n = 1.5 (min size) V DD = 2.5V V M  1.25V, g = -27.5 V IL = 1.2V, V IH = 1.3V NM L = NM H = 1.2 (actual values are V IL = 1.03V, V IH = 1.45V NM L = 1.03V & NM H = 1.05V) Output resistance low- output = 2.4k  high-output = 3.3k 

34. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Gain Determinates V in gain Gain is a strong function of the slopes of the currents in the saturation region, for V in = V M (1+r) g  ---------------------------------- (V M -V Tn -V DSATn /2)( n - p ) Determined by technology parameters, especially channel length modulation ( ). Only designer influence through supply voltage and V M (transistor sizing).

35. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Impact of Process Variation on VTC Curve V in (V) V out (V) Nominal Good PMOS Bad NMOS Bad PMOS Good NMOS lProcess variations (mostly) cause a shift in the switching threshold A good device has a small oxide thickness (-3nm), a small length (-25nm), a higher width (+30nm) and a smaller threshold (-60mV). The opposite is true for a bad device.

36. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Scaling the Supply Voltage V in (V) V out (V) Device threshold voltages are kept (virtually) constant V in (V) V out (V) Gain=-1 Device threshold voltages are kept (virtually) constant

37. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Next Time: CMOS Inverter max Layout V DD GND NMOS (2/.24 = 8/1) PMOS (4/.24 = 16/1) metal2 metal1 polysilicon In Out metal1-poly via metal2-metal1 via metal1-diff via pdiff ndiff

38. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Simplified CMOS Inverter Process cut line p well

39. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 P-Well Mask

40. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Contact Mask

41. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 Layout Editor: max Design Frame

42. Norhayati Soin 05 KEEE 4425 WEEK 3/2 7/29/2005 max Layer Representation Metals (five) and vias/contacts between the interconnect levels –Note that m5 connects only to m4, m4 only to m3, etc., and m1 only to poly, ndif, and pdif –Some technologies support “stacked vias” Wells (nw) and other select areas (pplus, nplus, prb) Active – active areas on/in substrate (poly gates, transistor channels (nfet, pfet), source and drain diffusions (ndif, pdif), and well contacts (nwc, pwc))