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CS 7960-4 Paper critiques: 25% of course grade Class participation: 5% Final exam: 20% Project: Simplescalar (?) modeling, simulation, and analysis: 50%

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Presentation on theme: "CS 7960-4 Paper critiques: 25% of course grade Class participation: 5% Final exam: 20% Project: Simplescalar (?) modeling, simulation, and analysis: 50%"— Presentation transcript:

1 CS 7960-4 Paper critiques: 25% of course grade Class participation: 5% Final exam: 20% Project: Simplescalar (?) modeling, simulation, and analysis: 50%

2 Superscalar Pipeline I - Cache PC BPred BTBBTB IFQ Rename Table ROBROB FU LSQ D-Cache checkpoints Issue queue op in1in2out FU Regfile

3 Rename A lr1  lr2 + lr3 B lr2  lr4 + lr5 C lr6  lr1 + lr3 D lr6  lr1 + lr2 RAR lr3 RAW lr1 WAR lr2 WAW lr6 A ; BC ; D pr7  pr2 + pr3 pr8  pr4 + pr5 pr9  pr7 + pr3 pr10  pr7 + pr8 RAR pr3 RAW pr7 WAR x WAW x AB ; CD

4 Resolving Branches A: lr1  lr2 + lr3 B: lr2  lr1 + lr4 C: lr1  lr4 + lr5 E: lr1  lr2 + lr3 D: lr2  lr1 + lr5 A: pr6  pr2 + pr3 B: pr7  pr6 + pr4 C: pr8  pr4 + pr5 E: pr10  pr7 + pr3 D: pr9  pr8 + pr5

5 Resolving Exceptions A lr1  lr2 + lr3 B lr2  lr1 + lr4 br C lr1  lr2 + lr3 D lr2  lr1 + lr5 pr6  pr2 + pr3 pr7  pr6 + pr4 br pr8  pr7 + pr3 pr9  pr8 + pr5

6 Resolving Exceptions A lr1  lr2 + lr3 B lr2  lr1 + lr4 br C lr1  lr2 + lr3 D lr2  lr1 + lr5 pr6  pr2 + pr3 pr7  pr6 + pr4 br pr8  pr7 + pr3 pr9  pr8 + pr5 A pr6 pr1 B pr7 pr2 C pr8 pr6 D pr9 pr7 ROB br

7 LSQ Ld/StAddressDataCompleted StoreUnknown1000-- Loadx40000000-- Storex50000000-- Loadx50000000-- Loadx30000000--

8 LSQ Ld/StAddressDataCompleted StoreUnknown1000-- Loadx40000000-- Storex50000000100Yes Loadx50000000-- Loadx30000000--

9 LSQ Ld/StAddressDataCompleted StoreUnknown1000-- Loadx40000000-- Storex50000000100Yes Loadx50000000100Yes Loadx30000000--

10 LSQ Ld/StAddressDataCompleted Storex450000001000Yes Loadx40000000-- Storex50000000100Yes Loadx50000000100Yes Loadx30000000-- can commit

11 LSQ Ld/StAddressDataCompleted Storex450000001000Yes Loadx4000000010Yes Storex50000000100Yes Loadx50000000100Yes Loadx300000001Yes

12 Instruction Wake-Up addp6p1p2 addp7 subp8 mulp9 addp10 p2p6 p1p2 p7p8 p1p7 p2

13 Topics ILP and technology trends (3) Clustered designs (2) Pipelining (1) Branch prediction and instruction fetch (3) Memory hierarchy (4) Register files (1) Power (3) SMT-CMP (4) Case studies (3) Reliability (1)

14 Next Week’s Paper “Limits of ILP”, David Wall, 1993 (print and read only the first 40 pages) What are the strengths of the paper? What are the weaknesses? How can such an evaluation be improved today? How can the lessons from this paper be applied to microprocessors today?

15 Title Bullet

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