1. Instruction Formats Competency: C5 Lecture no. 24

2. Basic Computer Instruction set Instructions 15 1412 110 I Opcode Address Memory-Reference Instructions (OP-code = 000 ~ 110) Register-Reference Instructions (OP-code = 111, I = 0) Input-Output Instructions(OP-code =111, I = 1) 1512 110 Register operation 0 1 1 1 1512 110 I/O operation 1 1

3. Instruction Formats Three-Address Instructions – ADDR1, R2, R3R3 ← [R1] + [R2] Two-Address Instructions – ADDR1, R2R2 ← [R1] + [R2] One-Address Instructions – ADDMAC ← AC + [M] Zero-Address Instructions – ADDTOS ← [TOS] + [(TOS – 1)] RISC Instructions – Lots of registers. Memory is restricted to Load & Store OpcodeOperand(s) or Address(es)

4. Instruction Formats Example: Evaluate X = (A+B)  (C+D) Three-Address 1.ADDA, B, R1; R1 ← [A] + [B] 2.ADDC, D, R2; R2 ← [C] + [D] 3.MULR1, R2, X; X ← [R1]  [R2]

5. Instruction Formats Example: Evaluate X = (A+B)  (C+D) Two-Address 1.MOVA, R1; R1 ← [A] 2.ADDB, R1; R1 ← [R1] + [B] 3.MOVC, R2; R2 ← [C] 4.ADDD, R2; R2 ← [R2] + [D] 5.MULR2, R1; R1 ← [R1]  [R2] 6.MOVR1, X; X ← [R1]

6. Instruction Formats Example: Evaluate X = (A+B)  (C+D) One-Address 1.LOADA; AC ← [A] 2.ADDB; AC ← [AC] + [B] 3.STORET; T ← [AC] 4.LOADC; AC ← [C] 5.ADDD; AC ← [AC] + [D] 6.MULT; AC ← [AC]  [T] 7.STOREX; X ← [AC]

7. Instruction Formats Example: Evaluate X = (A+B)  (C+D) Zero-Address 1.PUSHA; TOS ← [A] 2.PUSHB ; TOS ← [B] 3.ADD; TOS ← [A] + [B] 4.PUSH C; TOS ← [C] 5.PUSHD; TOS ← [D] 6.ADD; TOS ← [C] + [D] 7.MUL; TOS ← (C+D)  (A+B) 8.POPX; X ← [TOS]

8. Instruction Formats Example: Evaluate X = (A+B)  (C+D) RISC 1.LOADA, R1; R1 ← [A] 2.LOADB, R2; R2 ← [B] 3.LOADC, R3; R3 ← [C] 4.LOADD, R4; R4 ← [D] 5.ADDR1, R2, R1; R1 ← [R1] + [R2] 6.ADDR3, R4, R3; R3 ← [R3] + [R4] 7.MULR1, R3, R1; R1 ← [R1]  [R3] 8.STORER1, X; X ← [R1]