1. Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edit9on Lecture 3 Chapter 1: Introduction Provided & Updated by Sameer Akram

2. 1.2 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Computer System Organization Computer-System Operation A modern general-purpose computer consists of one or more CPUs and a number of device controllers connected through common bus that provides access to shared memory. Each device controller is in charge of a particular device type. CPU(s) and the devices controllers can execute in parallel, competing for memory cycles.

3. 1.3 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Computer System Organization Computer-system operation To ensure orderly access to the shared memory, a memory controller synchronizes access to the memory.

4. 1.4 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Computer-System Operation Each device controller is in charge of a particular device type. Depending on the controller, more than one devices can be attached to it. Each device controller maintains some local buffer storage and a set of special-purpose registers. I/O is from the device to local buffer of controller. The device controller is responsible for moving the data between the peripheral devices that it controls and its local buffer storage. Operating systems have a device driver for each device controller. This device driver understands the device controller and provides the rest of the operating system with a uniform interface to the device.

5. 1.5 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Computer-System Operation To start an I/O operation, the device driver loads the appropriate registers within the device controller. The device controller, in turn, examines the contents of these registers to determine what action to take (such as “read a character from the keyboard”). The controller starts the transfer of data from the device to its local buffer. Once the transfer of data is complete, the device controller informs the device driver via an interrupt that it has finished its operation. Device controller informs CPU that it has finished its operation by causing an interrupt. CPU moves data from/to main memory to/from local buffers.

6. 1.6 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Common Functions of Interrupts Interrupt transfers control to the interrupt service routine generally, through the interrupt vector, which contains the addresses of all the service routines Interrupt architecture must save the address of the interrupted instruction A trap or exception is a software-generated interrupt caused either by an error or a user request An operating system is interrupt driven

7. 1.7 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Common Functions of Interrupts (Stepwise) Interrupt occurs. Save state of the currently executed process into its PCB (Process Control Block). CPU → IVT (Interrupt Vector Table) to obtain the address of corresponding ISR. IVT: A table of pointers to ISRs (Interrupt Service Routines) / contains the addresses of all the service routines. This array, or interrupt vector, of addresses is indexed by a unique device number, given with interrupt request, to provide the address of the ISR for the interrupting device. (Operating systems different as Windows and UNIX dispatch interrupts in this manner.) Execute ISR. After the interrupt is serviced, the saved return address is loaded into the program counter, and the interrupted computation resumes as though the interrupt had not occurred.

8. 1.8 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Interrupt Handling The operating system preserves the state of the CPU by storing registers and the program counter Determines which type of interrupt has occurred: polling vectored interrupt system Separate segments of code determine what action should be taken for each type of interrupt

9. 1.9 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Interrupt Timeline

10. 1.10 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Direct Memory Access Structure Used for high-speed I/O devices able to transmit information at close to memory speeds Device controller transfers blocks of data from buffer storage directly to main memory without CPU intervention Only one interrupt is generated per block, rather than the one interrupt per byte

11. 1.11 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition How a Modern Computer Works A von Neumann architecture