1. ECE 554 Miniproject Spring 2002 www.engr.wisc.edu/ece/courses/ece554.html

2. OBJECTIVES To get familiar with the lab environment prior to the class project To provide the basic I/O interface to the class project

3. Configuration Download

4. XSV Board

5. XSV Block Diagram

6. XSV Board: Features Xilinx Virtex FPGA (Compute) 2 MB Memory (Store for Read/Write) Parallel & Serial Ports to PC (I/O from/to Outside World) Keyboard (PS/2) Port VGA Output to VGA Monitor Audio/Video Converter

7. Current Setup Parallel Cable Serial Cable NT machine running HyperTerminal Parallel port: Configuration download Serial port: Miniproject

8. Asynch Serial Communication Start bit (1 bit wide) Data bits (8 bits) Parity(None, Even, Odd) Stop bit (1 bit wide)

9. Baudrate and Sampling 4800 and 9600 bit per second Sampling rate = x16 of the baud rate (bit rate) Divide the clock (5 and 20 MHz) to get the “Enable” signal (sampling rate)

10. Transmitting Tx must be tested first. Tx shifts the “LSB” out from Tx buffer first. Tx sends “stop bit” when there is nothing to send.

11. Receiving Receiver samples the RxD to get the beginning of the “start bit” Use “resynchronization” to avoid “metastability” of any flip-flop

12. Processor Interface Data is sent/received across the “bidirectional” data bus Handshaking (status) signals TBR: Transmit Buffer Ready (Empty) RDA: Receive Data Available CS: Chip Select R/W_: Read or Write Bar signal

13. Testbench (mock Processor) A finite state machine Receives data on the RxD and transmits back on the TxD (echos) back to the HyperTerminal Note that it is not provided.

14. Demonstration