1. 1 COMP541 First Midterm Test Feb 22, 2007 2-3:15pmSN006 Vishal will be present

2. 2Syllabus  Syllabus: Everything covered in until Feb 15 Chapters 1-4, 6, 7 in textbook Chapters 1-4, 6, 7 in textbook Class notes Class notes Labs Labs  Test will be open book, notes, and calculator No computer (no Verilog simulator or tools, etc.) No computer (no Verilog simulator or tools, etc.)  Problems at same level as homework and labs

3. 3 Chapter 1  Binary and hexadecimal numbers  Binary addition, etc.  Parity

4. 4 Chapter 2  2-1, 2-2 Boolean algebra  Schematic diagrams  2-3 Basic Simplification Basic Boolean transformations Basic Boolean transformations  No Karnaugh maps  Gate types, 2-7, 2-8, 2-9

5. 5 Chapter 3  Basic circuit design Hierarchies Hierarchies  Gate delays  3-1, 3-2  We deferred most of chapter till later, so not included on this test

6. 6 Chapter 4  Know what encoder, decoder, and mux are  How to design them Logic Logic Verilog Verilog  Verilog styles (structural, dataflow, behavioral)  Be able to write combinational Verilog programs in structural and dataflow  4-1 through 4-5, 4-8

7. 7 Chapter 6  Basic latches  Flip flops Pulse Pulse Edge triggered most important Edge triggered most important  State machines  Verilog to represent flip flops and state machines  Sections 6-1 through 6-5, and 6-8

8. 8 Chapter 7  Registers  Counters  Shift registers  We have not looked at register transfer notation (or RTL), so not included on this test  Verilog to represent registers, counters, and shift registers  7-1, 7-6, and 7-11