1. FPGA BASED REAL TIME VIDEO PROCESSING Characterization presentation Presented by: Roman Kofman Sergey Kleyman Supervisor: Mike Sumszyk

2. AGENDA Project ObjectivesAlgorithmHardware ConsiderationsBasic Block DiagramDesign FlowTimeline

3. Project Objectives Improve video quality Study Non linear Diffusion algorithm Adjust algorithm to real time demands Implement on ProcstarII board with Altera’s FPGA Display real time results

4. Algorithm Based on the 2D non-linear Diffusion equation Iterative solution. Good Filtering – smoothes noises. Keeps borders intact.

5. Matlab simulation Original image Filtered image Good filteringKeeps borders intact dt=4, 4 iterations

6. Explicit Semi implicit Stable for small time steps. Good results requires many iterations. Simple implementation. Stable for all time steps. Good results after several iterations. High computational and storage effort (Thomas). Schemes

7. Thomas Inverts three diagonal matrixMakes real time implementation hard.

8. dt=0.5, 50 iterations dt=5, 5 iterations Original image

9. 10 iterations 20 iterations50 iterations dt=1.1

10. Hardware considerations DVI protocol defines minimum clock rate - 25.175Mhz, both input and output. The algorithm forces frame storage and the FPGA’s internal memory is not sufficient. Using onboard DDRII.Multiple Pipeline implementation.Each iteration multiplies the needed logic.

11. Basic Block Diagram DVI IN Implementation with internal pipeline On-board memory blocks DVI OUT ProcStarII board Daughter board PROC MultiPORT

12. Design Flow Synthesis and “Place and route” SinplifyPRO, ProcWizard, Quartus RTL generation Target selection and architectural optimizations Design entry and simulation Design and simulate algorithm with sinplifyDSP blocks.

13. Timeline 31.524.517.510.53.526.4. Algorithm study Fixed point adjustment Design Architecture Study the use of ProcStarII DDRII memory and run a read/write simulation. Implement dataflow path