1. MonolithIC 3D  Inc. Patents Pending 1 Precision Bonders - A Game Changer for Monolithic 3D DISRUPTOR A DISRUPTOR TO THE SEMICONDUCTOR INDUSTRY Paper 11.3 IEEE S3S October 2014 Zvi Or-Bach, Brian Cronquist, Zeev Wurman, Israel Beinglass, and Albert Henning MonolithIC 3D Inc.

2. Agenda  Motivation – The Escalating Challenges of 2D Scaling  Monolithic 3D as the Solution  Emerging Precision Bonders  Impact and a Process Flow  Advantages of Monolithic 3DIC 2

5. Connectivity Consumes 70-80% of Total Power @ 22nm Repeaters Consume Exponentially More Power and Area MonolithIC 3D  Inc. Patents Pending Source: IBM POWER processors R. Puri, et al., SRC Interconnect Forum, 2006  At 22nm, on-chip connectivity consumes 70-80% of total power  Repeater count increases exponentially  At 45nm, repeaters are > 50% of total leakage

6. “CEA-Leti Signs Agreement with Qualcomm to Assess Sequential (monolithic)3D Technology” Business Wire December 08, 2013 “Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law.” Geoffrey Yeap, VP of Technology at Qualcomm, Invited paper, IEDM 2013

8. 8 10,000 MONOLITHIC 10,000x the Vertical Connectivity of TSV

9. 9  Processing on top of copper interconnects should not make the copper interconnect exceed 400 o C  How to bring mono-crystallized silicon on top at less than 400 o C  How to fabricate state-of-the-art transistors on top of copper interconnect and keep the interconnect below at less than 400 o C  Misalignment of pre-processed wafer to wafer bonding step is was ~1µm  How to achieve 100nm or better connection pitch  How to fabricate thin enough layer for inter-layer vias of ~50nm The Monolithic 3D Challenge Why is it not already in wide use?

10. MonolithIC 3D - Precision Bonder Flow  RCAT (2009) – Process the high temperature on generic structures prior to ‘smart-cut’, and finish with cold processes – Etch & Depositions  Gate Replacement (2010) (=Gate Last, HKMG) - Process the high temperature on repeating structures prior to ‘smart- cut’, and finish with ‘gate replacement’, cold processes – Etch & Depositions  Laser Annealing (2012) – Use short laser pulse to locally heat and anneal the top layer while protecting the interconnection layers below from the top heat  Precise Bonder (2014) – Use precision bonder and prior techniques such as ‘gate replacement’. Offers low cost flow with minimal R&D

11. Precision Bonder – Breakthrough With MonolthIC 3D flow => Easy path to M3D  Alignment challenge is resolved by the use of Precision Bonder and ‘Smart Alignment’  Achieving 10,000x vertical connectivity as the upper strata will be thinner than 100 nm  Rich vertical connectivity  High performance – low vertical connection RC  Low manufacturing costs  Utilizing the existing front-end process !!! Patents Pending

12. 12 ~700 µm Donor Wafer Use standard flow to process “Stratum 3” PMOS NMOS Silicon Poly Oxide STI Stratum 3 Patents Pending

13. 13 ~700µm Donor Wafer PMOSNMOS Silicon Implant H+ 100nm depth for the ion-cut H+ STI ~100nm Ions Implant ~E 17 Patents Pending

14. 14 ~700µm Donor Wafer Silicon Bond to a carrier-wafer H+ ~700µm Carrier Wafer STI Oxide to Oxide bond Patents Pending

15. 15 ~700µm Donor Wafer ‘Cut’ (Heating to ~550 ºC) Donor Wafer off H+ ~700µm Carrier Wafer Transferred ~100nm Layer - Stratum 3 Silicon STI Patents Pending

16. 16 CMP and repair the transferred layer – high temperature is OK ! ~700µm Carrier Wafer ~100nm STI Silicon Oxide Bond Oxide ’etch stop’ Patents Pending

17. 17 Use standard flow to process “Stratum 2” Note: High Temperature is OK Note: A vertical isolation could be formed by reverse bias, deep implant or other methods. ~700µm Carrier Wafer ~100nm Layer Silicon Oxide Bond Oxide ’etch stop’ STI High Performance Transistors Oxide Stratum 2 Stratum 3 Patents Pending

18. 18 Add at least one interconnect layer ~700µm Carrier Wafer ~100nm Transferred Layer Silicon Oxide Bond Oxide ’etch stop’ Stratum 2 Stratum 3 Patents Pending

19. MonolithIC 3D Inc. Patents Pending 19 Transfer onto target layer ~700µm Carrier Wafer Oxide-oxide bond Transferred Layer (Stratum 2 +Stratum 3) Base Wafer PMOS NMOS Patents Pending

20. MonolithIC 3D Inc. Patents Pending 20 Remove carrier-wafer (grind, etch) ~700µm Carrier Wafer Oxide-oxide bond Base Wafer PMOS NMOS Stratum 3 Stratum 2 100 nm Patents Pending

21. MonolithIC 3D Inc. Patents Pending 21 Gate replacements (when applicable) Oxide-oxide bond PMOS NMOS Stratum 2 Base Wafer Stratum 3 Patents Pending

22. Monolithic 3D using Precise Bonder  Utilizes existing transistor process  Could help upgrade any fab (leading or trailing)  Provides two additional transistor layers  Very competitive cost structure  Better power, performance, price than a node of scaling at a fraction of the costs !!!  Allows functionality that could not be attained by 2D devices

23. 23 Connect to “Strata 1” using ‘Smart-Alignment ’ Bottom layer layout Top layer layout Landing pad Through- layer connection Oxide ‘Smart-Alignment’ Patents Pending

24. Smart Alignment 200nm Through Layer Via connected by landing pad of 200x200 nm²

25. Smart Alignment

26. 26 ‘Smart-Alignment’ Bottom layer layout Landing pad Vertical connection 1 for 200nmx200nm Vertical connection 200nm/metal pitch ~ 20 for 200nmx200nm  ~20X better vertical connectivity  Minimum abstraction for routing ‘Smart-Alignment’ Patents Pending

27. Sequential vs. Parallel  Some people call monolithic 3D as a ‘sequential process’ in contrast to TSV which is ‘parallel’  Sequential process might over-extend TAT !  By using the MonolithIC + Fusion Bonder flow, a parallel monolithic flow could be constructed Patents Pending

28. 1.Reduction die size and power – doubling transistor count - Extending Moore’s law Monolithic 3D is far more than just an alternative to 0.7x scaling !!! 2. Significant advantages from using the same fab, design tools 3. Heterogeneous Integration 4. Multiple layers Processed Simultaneously - Huge cost reduction (Nx)  Logic redundancy => 100x integration made possible  3D FPGA prototype, 2D volume 7. Enables Modular Design 8.Naturally upper layers are SOI 9.Local Interconnect above and below transistor layer 10.Re-Buffering global interconnect by upper strata 11.Others A. Image sensor with pixel electronics B. Micro-display The Monolithic 3D Advantage

29. Some 3D Applications  Image sensor with pixel electronics  3D FPGA  Ultra Scale integration using M3DI Redundancy  1T SRAM (Zeno) over Logic  I/O-SRAM-Logic

30. 1T SRAM (Zeno) over FinFET

31. Image Sensor with Pixel Electronics  With rich vertical connectivity, every pixel of an image sensor could have its own pixel electronics underneath Patents Pending

32. The Twin - Field-programmable & via-configurable fabric Prototype Phase-3D Production Phase-2D Prototype volumes Prototype costs Std. logic w/mono-3D Production volumes Production costs Standard logic process 1-Mask customization Backup-foundry capable Anti-fuses HV Programming Transistors Vp OTP till design & functions stabilized Specific foundry Patents Pending

33. FPGA Achilles’ Heel – PIC (Programmable Interconnect) >30x Area vs. Antifuse/Masked Via Average area ratio of connectivity element > 30 Current FPGAs use primarily pass transistors with a driver. Via Pitch - 0.2 .2 x.2= 0.04  2 Area: 0.04  2 SRAM FPGA connectivity elements @ 45 nm Via connectivity element @ 45 nm.2  SRAM bit SRAM bit SRAM bit SRAM bit Bidi buffer Area  4  2 Ratio to AF  100 TS buffer Area  2  2 Ratio to AF  50 Pass gate Area .5  2 Ratio to AF  12 4X 10X 4X.2  Via/AF

34. Innovation Enabling ‘Wafer Scale Integration’ – 99.99% Yield with 3D Redundancy  Swap at logic cone granularity  Negligible design and power penalty  Redundant 1  above, no performance penalty Gene Amdahl -“Wafer scale integration will only work with 99.99% yield, which won’t happen for 100 years” (Source: Wikipedia)  Server-Farm in a Box  Watson in a Smart Phone  … Patents Pending

35. V. Multiple Layers Processed Simultaneously - Huge Cost Reduction (Nx) –”BICS ”  Multiple thin layers can be process simultaneously, forming transistors on multiple layers  Cost reduction correlates with number of layers being simultaneously processed (2, 4, 8, 16, 32, 64, 128,...)

36. IV. Heterogeneous Integration  Logic, Memories, I/O on different strata  Optimized process and transistors for the function  Optimizes the number of metal layers  Optimizes the litho. (spacers, older node)  Low power, high speed (sequential, combinatorial)  Different crystals – E/O

37. VII. Enables Modular Design  Platform-based design could evolve to:  Few layers of generic functions like compute, radios, and one layer of custom design  Few layers of logic and memories and one layer of FPGA ...

38. Summary  We have reached an inflection point  Monolithic 3D IC – The next generation technology driver  Breaking News – The barriers are now removed  Multiple simple and practical paths to monolithic 3D exist  Monolithic 3D provides more than just scaling

39. Backup 39

40. The Operational Thermal Challenge  Upper tier transistors are fully surrounded by oxide and have no thermal path to remove operational heat away Good Heat Conduction ~100 W/mK Poor Heat Conduction ~1 W/mK

41. Cooling Three-Dimensional Integrated Circuits using Power Delivery Networks (PDNs) Hai Wei, Tony Wu, Deepak Sekar +, Brian Cronquist*, Roger Fabian Pease, Subhasish Mitra Stanford University, Rambus +, Monolithic 3D Inc.* 41 IEDM 2012 Paper

42. Monolithic 3D Heat Removal Architecture ( Achievable with Monolithic 3D vertical interconnect density)  Global power grid shared among multiple device layers, local power grid for each device layer  Local V DD grid architecture shown above  Optimize all cells in library to have low thermal resistance to V DD /V SS lines (local heat sink) pxpx pypy Without Power Grid With Power Grid Signal wire Heat sink Patents Pending