1. CS 61C L5.1.2 CPU Design II (1) K. Meinz, Summer 2004 © UCB CS61C : Machine Structures Lecture 5.1.2 CPU Design II 2004-07-20 Kurt Meinz inst.eecs.berkeley.edu/~cs61c

2. CS 61C L5.1.2 CPU Design II (2) K. Meinz, Summer 2004 © UCB Anatomy: 5 components of any Computer Personal Computer Processor Computer Control (“brain”) Datapath (“brawn”) Memory (where programs, data live when running) Devices Input Output Keyboard, Mouse Display, Printer Disk (where programs, data live when not running) This week

3. CS 61C L5.1.2 CPU Design II (3) K. Meinz, Summer 2004 © UCB Step 1: Abstract Implementation Data Out Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions

4. CS 61C L5.1.2 CPU Design II (4) K. Meinz, Summer 2004 © UCB Step 2b: Components of the Datapath Combinational Elements Storage Elements Clocking methodology

5. CS 61C L5.1.2 CPU Design II (5) K. Meinz, Summer 2004 © UCB Storage Element: Idealized Memory Memory (idealized) One input bus: Data In One output bus: Data Out Memory word is selected by: Address selects the word to put on Data Out Write Enable = 1: address selects the memory word to be written via the Data In bus Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: -Address valid => Data Out valid after “access time.” Clk Data In Write Enable 32 DataOut Address

6. CS 61C L5.1.2 CPU Design II (6) K. Meinz, Summer 2004 © UCB Verilog Memory for MIPS Interpreter (1/3) //Behavioral modelof Random Access Memory: // 32-bit wide, 256 words deep, // asynchronous read-port if RD=1, // synchronous write-port if WR=1, // initialize from hex file ("data.dat") // on positive edge of reset signal, // dump to binary file ("dump.dat") // on positive edge of dump signal. module mem (CLK,RST,DMP,WR,RD,address,writeD,readD); input CLK, RST, DMP, WR, RD; input [31:0] address, writeD; output [31:0] readD; reg [31:0] readD; parameter memSize=256; reg [31:0] memArray [0:memSize-1]; integer chann,i;

7. CS 61C L5.1.2 CPU Design II (7) K. Meinz, Summer 2004 © UCB Verilog Memory for MIPS Interpreter (2/3) integer chann,i; always @ (posedge RST) $readmemh("data.dat", memArray); always @ (posedge CLK) if (WR) memArray[address[9:2]] = writeD; always @ (address or RD)* if (RD) readD = memArray[address[9:2]]; endmodule // write if WR & positive clock edge (synchronous) // read if RD, independent of clock (asynchronous)  See how sneaky sensitivity lists can be! Use an assign!

8. CS 61C L5.1.2 CPU Design II (8) K. Meinz, Summer 2004 © UCB Why is it “ memArray[address[9:2]] ”? Our memory is always byte-addressed We can lb from 0x0, 0x1, 0x2, 0x3, … lw only reads word-aligned requests We only call lw with 0x0, 0x4, 0x8, 0xC, … I.e., the last two bits are always 0 memArray is a word wide and 2 8 deep reg [31:0] memArray [0:256-1]; Size = 4 Bytes/row * 256 rows = 1024 B If we’re simulating lw/sw, we R/W words What bits select the first 256 words? [9:2]! 1 st word = 0x0 = 0b000 = memArray[0]; 2 nd word = 0x4 = 0b100 = memArray[1], etc.

9. CS 61C L5.1.2 CPU Design II (9) K. Meinz, Summer 2004 © UCB Verilog Memory for MIPS Interpreter (3/3) end; always @ (posedge DMP) begin chann = $fopen("dump.dat"); if (chann==0) begin $display("$fopen of dump.dat failed."); $finish; end for (i=0; i<memSize; i=i+1) begin $fdisplay(chann, "%b", memArray[i]); end end // always @ (posedge DMP) endmodule // mem // Temp variables chan, i

10. CS 61C L5.1.2 CPU Design II (10) K. Meinz, Summer 2004 © UCB Storage Element: Register (Building Block) 32-bit Register Similar to the D Flip Flop except -N-bit input and output -Write Enable input (CE) Write Enable: -negated (or deasserted) (0): Data Out will not change -asserted (1): Data Out will become Data In Clk Data In Write Enable NN Data Out

11. CS 61C L5.1.2 CPU Design II (11) K. Meinz, Summer 2004 © UCB Verilog 32-bit Register // Behavioral model of 32-bit Register: // positive edge-triggered, // synchronous active-high reset. module reg32 (CLK,Q,D,RST); input [31:0] D; input CLK, RST; output [31:0] Q; reg [31:0] Q; always @ (posedge CLK) if (RST) Q = 0; else Q = D; endmodule // reg32

12. CS 61C L5.1.2 CPU Design II (12) K. Meinz, Summer 2004 © UCB Storage Element: Register File Register File consists of 32 registers: Two 32-bit output busses: busA and busB One 32-bit input bus: busW Register is selected by: RA (number) selects the register to put on busA (data) RB (number) selects the register to put on busB (data) RW (number) selects the register to be written via busW (data) when Write Enable is 1 Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: -RA or RB valid => busA or busB valid after “access time.” Clk busW Write Enable 32 busA 32 busB 555 RWRARB 32 32-bit Registers

13. CS 61C L5.1.2 CPU Design II (13) K. Meinz, Summer 2004 © UCB Verilog Register File (1/4) // Behavioral model of register file: // 32-bit wide, 32 words deep, // two asynchronous read-ports, // one synchronous write-port. // Dump register file contents to // console on pos edge of dump signal.

14. CS 61C L5.1.2 CPU Design II (14) K. Meinz, Summer 2004 © UCB module regFile (CLK, wEnb, DMP, writeReg, writeD, readReg1, readD1, readReg2, readD2); input CLK, wEnb, DMP; input [4:0] writeReg, readReg1, readReg2; input [31:0] writeD; output [31:0] readD1, readD2; reg [31:0] readD1, readD2; reg [31:0] array [0:31]; reg dirty1, dirty2; integer i; 3 5-bit fields to select registers: 1 write register, 2 read register Verilog Register File (2/4)

15. CS 61C L5.1.2 CPU Design II (15) K. Meinz, Summer 2004 © UCB Verilog Register File (3/4) always @ (posedge CLK) if (wEnb) if (writeReg!=5'h0) // why? begin array[writeReg] = writeD; dirty1=1'b1; //why? dirty2=1'b1; end always @ (readReg1 or dirty1) begin readD1 = array[readReg1]; dirty1=0; end

16. CS 61C L5.1.2 CPU Design II (16) K. Meinz, Summer 2004 © UCB Verilog Register File (4/4) Problem 1: dirty1 is awful!! assign readD2 = array[readReg2]; Problem 2: Synchronous reads? - must happen on posedge - must get new value if written always @ (posedge clock) if (readReg2 == writeReg) readD2 = writeD; //”forwarding”! else readD2 = array[readReg2];  Can you see the bug?

17. CS 61C L5.1.2 CPU Design II (17) K. Meinz, Summer 2004 © UCB How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) => datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic (hard part!)

18. CS 61C L5.1.2 CPU Design II (18) K. Meinz, Summer 2004 © UCB Step 3: Assemble DataPath meeting requirements Register Transfer Requirements  Datapath Assembly Dataflow: (Functional Union of all ISA ops) Instruction Fetch IF Read Operands DE ALU Operation (if necessary) EX Memory Operation (if necessary) MEM Write back to Registers (if necessary) WB

19. CS 61C L5.1.2 CPU Design II (19) K. Meinz, Summer 2004 © UCB Step 3: Abstract Implementation Data Out Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions IF DE EX MEM WB

20. CS 61C L5.1.2 CPU Design II (20) K. Meinz, Summer 2004 © UCB 3a: IF: Instruction Fetch The common RTL operations Fetch the Instruction: mem[PC] Update the program counter: -Sequential Code: PC = PC + 4 -Branch and Jump: PC = “something else” 32 Instruction Word Address Instruction Memory PCClk Next Address Logic

21. CS 61C L5.1.2 CPU Design II (21) K. Meinz, Summer 2004 © UCB 3a: DE: Decode (Read Operands) R[rd] = R[rs] op R[rt] Ex.: addU rd, rs, rt Ra, Rb, and Rw come from instruction’s Rs, Rt, and Rd fields oprsrtrdshamtfunct 061116212631 6 bits 5 bits Clk 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRt IF and DE are held in common for all ops. Now, we split up behavior by op type …

22. CS 61C L5.1.2 CPU Design II (22) K. Meinz, Summer 2004 © UCB 3b: Add & Subtract R[rd] = R[rs] op R[rt] Ex.: addU rd, rs, rt ALUctr and RegWr: control logic after decoding the instruction 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU Already defined register file, ALU

23. CS 61C L5.1.2 CPU Design II (23) K. Meinz, Summer 2004 © UCB Register-Register Timing: One complete cycle 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU Clk PC Rs, Rt, Rd, Op, Func ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA, B Register File Access Time Old ValueNew Value busW ALU Delay Old ValueNew Value Old ValueNew Value Old Value Register Write Occurs Here

24. CS 61C L5.1.2 CPU Design II (24) K. Meinz, Summer 2004 © UCB 3c: Logical Operations with Immediate R[rt] = R[rs] op ZeroExt[imm16] 32 Result ALUct r Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs ZeroExt Mux RtRd RegDst Mux 32 16 imm16 ALUSrc ALU 11 oprsrtimmediate 016212631 6 bits16 bits5 bits rd? immediate 0161531 16 bits 0 0 0 0 0 0 0 0 Rt? Already defined 32-bit MUX; Zero Ext? What about Rt register read??

25. CS 61C L5.1.2 CPU Design II (25) K. Meinz, Summer 2004 © UCB 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs RtRd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory 32 ALU MemWr Mu x W_Src ?? Rt?

26. CS 61C L5.1.2 CPU Design II (26) K. Meinz, Summer 2004 © UCB 3e: Store Operations Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory MemWr ALU 32 Mu x W_Src

27. CS 61C L5.1.2 CPU Design II (27) K. Meinz, Summer 2004 © UCB 3f: The Branch Instruction beqrs, rt, imm16 mem[PC]Fetch the instruction from memory Equal = R[rs] == R[rt]Calculate the branch condition if (Equal) Calculate the next instruction’s address -PC = PC + 4 + ( SignExt(imm16) x 4 ) else -PC = PC + 4 oprsrtimmediate 016212631 6 bits16 bits5 bits

28. CS 61C L5.1.2 CPU Design II (28) K. Meinz, Summer 2004 © UCB Datapath for Branch Operations beq rs, rt, imm16 Datapath generates condition (equal) oprsrtimmediate 016212631 6 bits16 bits5 bits 32 imm16 PC Clk Adder Mux Adder 1 nPC_sel Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Equal? Cond PC Ext Inst Address Already MUX, adder, sign extend, zero 00

29. CS 61C L5.1.2 CPU Design II (29) K. Meinz, Summer 2004 © UCB Putting it All Together:A Single Cycle Datapath imm16 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal Instruction 0 1 0 1 0 1 Imm16RdRtRs = Adder PC Clk Mux 1 nPC_sel PC Ext Adr Inst Memory 00

30. CS 61C L5.1.2 CPU Design II (30) K. Meinz, Summer 2004 © UCB Recall: Clocking Methodology All storage elements are clocked by the same clock edge Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew Clk Don’t Care SetupHold........................ SetupHold

31. CS 61C L5.1.2 CPU Design II (31) K. Meinz, Summer 2004 © UCB Clocking Methodology Storage elements clocked by same edge Being physical devices, flip-flops (FF) and combinational logic have some delays Gates: delay from input change to output change Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF, and we have the usual clock-to-Q delay “Critical path” (longest path through logic) determines length of clock period Clk........................

32. CS 61C L5.1.2 CPU Design II (32) K. Meinz, Summer 2004 © UCB An Abstract View of the Implementation Data Out Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions

33. CS 61C L5.1.2 CPU Design II (33) K. Meinz, Summer 2004 © UCB An Abstract View of the Critical Path Critical Path (Load Operation) = Delay clock through PC (FFs) + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Stable Time for Register File Write Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 16 Imm 32 A B Next Address This affects how much you can overclock your PC!