1. 5 - 1 Chapter 6 Analysis of Sequential Systems

2. 5 - 2 Chapter 6 Analysis of Sequential Systems 6.0 Introduction  Clocked System Clock A signal that alternates between 0 and 1 at a regular rate Two versions of clock Type A : 0 half and 1 half Type B : 1 is shorter part of the cycle P. 277

3. 5 - 3 Chapter 6 Analysis of Sequential Systems 6.0 Introduction  Synchronous System Change occurs on the transition of the clock signal Conceptual view of a synchronous sequential system n inputs(x’s), clock, k outputs(z’s), m binary storage devices(q’s) P. 278

4. 5 - 4 Chapter 6 Analysis of Sequential Systems 6.1 State Tables and Diagrams  CE6 A system with one input x and one output z such that z = 1 iff x has been 1 for at least three consecutive clock times. State The last three inputs store in memory Timing Trace A Set of values for the input and the output at consecutive clock times x011011100101111100 z?00000010000001110000 P. 279

5. 5 - 5 Chapter 6 Analysis of Sequential Systems 6.1 State Tables and Diagrams  CE6 Moore Model The output depends only on the state of the system. The output occurs after the desired input pattern has occurred. Named after E. F. Moore. The output for the first input is shown as unknown. After 3 consecutive inputs are 1, the system output is 1. x011011100101111100 z?00000010000001110000 P. 278

6. 5 - 6 Chapter 6 Analysis of Sequential Systems 6.1 State Tables and Diagrams  Two Tools for Describing Sequential Systems State Table It shows the output and the next state for each input combination and each state. Next state is to be stored in memory after the next clock. State Diagram(State Graph) A graphical representation of the behavior of the system. State Table State Diagram Present state Next state x=0 x=1 Present output A AB 0 B AC 0 C AD 0 D AD 1 P. 280

7. 5 - 7 Chapter 6 Analysis of Sequential Systems 6.1 State Tables and Diagrams  Two Tools for Describing Sequential Systems Representation q : present state q* : next state ( Q, q+, q+  ) It will be stored in memory after this clock transition Output depends on the present state, but not the present input. State Diagram corresponds to its state table. Trace with State x0110111001011111100 q?ABCABCDAABABCDDDDAA? z?000000100000011110000 P. 281

8. 5 - 8 Chapter 6 Analysis of Sequential Systems 6.1 State Tables and Diagrams  Mealy Model The Output depends not only the present state of the machine, but also on the present input. The state table has as many output columns as the next state portion. The state diagram is different from the Moore model. State TableState Diagram Trace with State q q* x=0 x=1 z x=0 x=1 AAB 0 0 BAC 0 0 CAC 0 1 x0110111001011111100 q?ABCABCCAABABCCCCCAA z?00000010000001111000 P. 281 - 282

9. 5 - 9 Chapter 6 Analysis of Sequential Systems 6.2 Latches  Latch Binary storage device composed of two or more gates with feedback. Simple example Simplest two NOR gates latch The output of each gate is connected to the input of the other gate. Equations for this system P = ( S + Q )’ Q = ( R + P )’ P. 282

10. 5 - 10 Chapter 6 Analysis of Sequential Systems 6.2 Latches  Latch Simple example Equations for this system S = 0, R = 0 P = Q’, Q = P’ Store 0 (Q = 0 and P = 1) or store 1 (Q = 1 and P = 0) S is used to indicate ‘set’, store a 1 in the latch S = 1, R = 0 P = (1 + Q)’ = 1’ = 0 Q = (0 + 0)’ = 0’ = 1 R is used to indicate ‘reset’, store a 0 in the latch S = 0, R = 1 Q = (1 + P)’ = 1’ = 0 P = (0 + 0)’ = 0’ = 1

11. 5 - 11 Chapter 6 Analysis of Sequential Systems 6.2 Latches  Latch Simple example Equations for this system S = 1, R = 1 : not operated P = (1 + Q)’ = 1’ = 0 Q = (1 + P)’ = 1’ = 0

12. 5 - 12 Chapter 6 Analysis of Sequential Systems 6.2 Latches  Gated Latch Gate signal is inactive ( = 0 )  SG, RG are both 0. Latch remains unchanged. Gate signal is active ( = 1 )  Latch stores 0 or 1. P. 283

13. 5 - 13 Chapter 6 Analysis of Sequential Systems 6.3 Flip Flops  Flip Flop Clocked binary storage device Flip Flop stores a 0 or a 1. Trailing-edge Triggered Change FF state when the clock goes from 1 to 0. Leading-edge Triggered Change FF state when the clock goes from 0 to 1. Various Types of Flip Flops D Flip Flop JK Flip Flop SR Flip Flop T Flip Flop

14. 5 - 14 Chapter 6 Analysis of Sequential Systems 6.3 Flip Flops  D Flip Flop The output is just the input delayed until the next active clock transition. Block Diagram D q q’ D q Clock Trailing-edge Triggered Leading-edge Triggered P. 284

15. 5 - 15 Chapter 6 Analysis of Sequential Systems 6.3 Flip Flops  D Flip Flop Two forms of a truth table State Diagram Dqq* 000 010 101 111 D 00 11 P. 284

16. 5 - 16 Chapter 6 Analysis of Sequential Systems 6.3 Flip Flops  D Flip Flop Timing Diagram Trailing-edge triggered D FF Result in (b) will be same as (a) (a) (b) P. 285

17. 5 - 17 Chapter 6 Analysis of Sequential Systems 6.3 Flip Flops  D Flip Flop Timing Diagram Leading-edge triggered D FF P. 286

18. 5 - 18 Chapter 6 Analysis of Sequential Systems 6.3 Flip Flops  D Flip Flop Two Flip Flops P. 286 - 287

19. 5 - 19 Chapter 6 Analysis of Sequential Systems 6.3 Flip Flops  D Flip Flop Preset and Reset P. 287

20. 5 - 20 Chapter 6 Analysis of Sequential Systems 6.3 Flip Flops  D Flip Flop Preset and Reset P. 288

21. 5 - 21 Chapter 6 Analysis of Sequential Systems 6.3 Flip Flops  SR(Set-Reset) Flip Flop Behavioral Tables SR Flip Flop State Diagram P. 288

22. 5 - 22 Chapter 6 Analysis of Sequential Systems 6.3 Flip Flops  SR(Set-Reset) Flip Flop Behavioral Map q* = S + R’q Timing Diagram q* P. 289

23. 5 - 23 Chapter 6 Analysis of Sequential Systems 6.3 Flip Flops  T(Toggle) Flip Flop T = 1, TFF changes state (Toggled). T = 0, TFF state remains same. Behavioral Table State Diagram Tqq* 000 011 101 110 T 0q 1q` P. 289

24. 5 - 24 Chapter 6 Analysis of Sequential Systems 6.3 Flip Flops  T(Toggle) Flip Flop Behavioral Equation q* = T q Timing Diagram P. 290

25. 5 - 25 Chapter 6 Analysis of Sequential Systems 6.3 Flip Flops  JK Flip Flop Combination of SR and T J = K = 1, FF changes state. Behavioral Table State Diagram P. 290

26. 5 - 26 Chapter 6 Analysis of Sequential Systems 6.3 Flip Flops  JK Flip Flop Behavioral Equation q* = Jq’ + K’q Timing Diagram P. 291

27. 5 - 27 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems  D Flip Flop Moore Model(1) Circuit Equation D 1 = q 1 q 2 ’ + xq 1 ’ D 2 = xq 1 z = q 2 ’ P. 292

28. 5 - 28 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems  D Flip Flop Moore Model(2) State Table Partial State Table Complete State Table Moore State Diagram P. 293

29. 5 - 29 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems  JK Flip Flop Moore Model(1) Circuit Equation J A = x K A = xB’ J B = K b = x + A’ z = A + B P. 293

30. 5 - 30 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems  JK Flip Flop Moore Model(2) State Table First two entries A* entered Complete State Table P. 294

31. 5 - 31 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems  JK Flip Flop Moore Model(3) State Table using Equation q* = Jq’ + K’q A* = J A A’ + K A ’A = xA’ + (xB’)A = xA’ + x’A + AB B* = J B B’ + K B ’B = (x + A’)B’ + (x + A’)’B = xB’ + A’B’ + x’AB State table can be constructed with D flip flops. These equations give exactly the same results as before. Trace Table P. 295

32. 5 - 32 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems  JK Flip Flop Moore Model(4) Timing Diagram P. 296

33. 5 - 33 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems  JK Flip Flop Moore Model(5) State Diagram P. 296

34. 5 - 34 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems  JK Flip Flop Mealy Model(1) Circuit Equations D 1 = xq 1 + xq 2 D 2 = xq 1 ’q 2 ’ z = xq 1 q 1 * = xq 1 + xq 2 q 2 * = xq 1 ’q 2 ’ P. 297

35. 5 - 35 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems  JK Flip Flop Mealy Model(2) State Table State Diagram P. 297 - 298

36. 5 - 36 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems  JK Flip Flop Mealy Model(3) Mealy Modeling Timing P. 298

37. 5 - 37 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems  JK Flip Flop Mealy Model(4) Timing Diagram P. 299

38. 5 - 38 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems Circuit Moore model Output z does not depend on the input x z = q 1 q 2 Example 6.1a(1) P. 299

39. 5 - 39 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems Equations J 1 = xq 2, K 1 = x’ D 2 = x(q 1 +q 2 ’) When x = 0, J 1 = 0, K 1 = 1, and D 2 = 0, thus system state is 00 When x = 1 J 1 = q 2, K 1 = 0, D 2 = q 1 + q 2 ’ q 1 * = xq 1 ’q 2 + xq 1 = x(q 1 + q 2 ) State Table Example 6.1a(2) P. 300

40. 5 - 40 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems Timing Diagram Example 6.1a(3) P. 300

41. 5 - 41 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems z = x’q 1 q 2 This machine is a Mealy model. State Diagram Example 6.1b P. 299, 301

42. 5 - 42 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems Assume initial state is 0000 J 1 = K 1 = xq 4 T 2 = q 1 ’ S 3 = q 2 ’, R 3 = q 2 D 4 = q 3 Example 6.2 P. 301

43. 5 - 43 Chapter 6 Analysis of Sequential Systems 6.4 Analysis of Sequential Systems q 1 : changes state only when xq 4 = 1 q 2 : changes state only when q 1 = 0 q 3 * = q 2 ’ q 4 * = q 3 Example 6.2 (cont.) x111011 q1q1 000110000 q2q2 0101110101 q3q3 01010001010 q4q4 001010001010 P. 302