1. Chieh Chang EE 235 – Presentation IMarch 20, 2007 Nanoimprint Lithography for Hybrid Plastic Electronics Michael C. McAlpine, Robin S. Friedman, and Charles M. Lieber Harvard UniVersity

2. Introduction Efficient fabrication of integrated circuits Efficient fabrication of integrated circuits Reliable Reliable High-throughput processing High-throughput processing Photolithography Photolithography Feature resolution: 100nm Feature resolution: 100nm Complex and costly fabrication equipment Complex and costly fabrication equipment Alternatives of nanoscale patterning Alternatives of nanoscale patterning Electron beam Electron beam Scanning probe Scanning probe Extreme ultraviolet Extreme ultraviolet Dip pen Dip pen Nanoimprint Nanoimprint Scalable, parallel, cost-effective Scalable, parallel, cost-effective Feature resolution: sub-25nm Feature resolution: sub-25nm

3. Nanoimprint Thermoplastic NIL Thermoplastic NIL Heating process limits the application to flexible plastic substract. Heating process limits the application to flexible plastic substract. NIL @ room temperature on plastic substrate with nanometer scale resolution NIL @ room temperature on plastic substrate with nanometer scale resolution Combined with inorganic semiconductor nanowires to generate nanoscale transistor Combined with inorganic semiconductor nanowires to generate nanoscale transistor

4. Schematic Plastic substrates coated with SiO 2 and Lift-off resistor (LOR) were imprinted using a Si/SiO2 stamp. Plastic substrates coated with SiO 2 and Lift-off resistor (LOR) were imprinted using a Si/SiO2 stamp. The NIL pattern was transferred to the substrate in successive RIE The NIL pattern was transferred to the substrate in successive RIE Metal deposition, and lift- off steps Metal deposition, and lift- off steps

5. Key Issues The deposition of a resistor for room temperature imprinting The deposition of a resistor for room temperature imprinting Reproducibly imprinted at room temperature Reproducibly imprinted at room temperature Cleanly removed from the inorganic stamp without antiadhesion agents Cleanly removed from the inorganic stamp without antiadhesion agents Etched at controlled rates by RIE Etched at controlled rates by RIE The SiO 2 The SiO 2 Improve metal adhesion Improve metal adhesion Not affect flexibility Not affect flexibility

6. Results (A) Optical image of S-D array and interconnect wires; scale bar, 100 um (A) Optical image of S-D array and interconnect wires; scale bar, 100 um (B) Optical image of 200 nm S- D lines and 1 um interconnect lines; scale bar, 25 um (B) Optical image of 200 nm S- D lines and 1 um interconnect lines; scale bar, 25 um (C) SEM image of S-D array of 2um pitch, and 500nm gap; scale bar,20 um (C) SEM image of S-D array of 2um pitch, and 500nm gap; scale bar,20 um (Inset) SEM image of 200 nm width channel lines; scale bar, 200nm (Inset) SEM image of 200 nm width channel lines; scale bar, 200nm

7. Results (D) Optical image of patterned Mylar substrate (D) Optical image of patterned Mylar substrate (E) Optical image of hierarchically patterned arrays of gate electrodes; scale bar, 100 um (E) Optical image of hierarchically patterned arrays of gate electrodes; scale bar, 100 um (Inset) SEM image of a gate array block, where corner squares are alignment marks; scale bar, 5 um (Inset) SEM image of a gate array block, where corner squares are alignment marks; scale bar, 5 um

8. Bottom-up + Top-down A solution of p-type SiNWs were flow- aligned in a direction perpendicular to the gate electrode arrays A solution of p-type SiNWs were flow- aligned in a direction perpendicular to the gate electrode arrays FET: 20 nm p-SiNW crossing an imprint- patterned metal gate FET: 20 nm p-SiNW crossing an imprint- patterned metal gate

9. Measurement Current versus S-D voltage (I-Vsd) data recorded on a typical crossed-junction p- SiNW FET. Current versus S-D voltage (I-Vsd) data recorded on a typical crossed-junction p- SiNW FET. The S-D contacts are ohmic. The S-D contacts are ohmic. As Vg is increased, the slopes of the individual I-Vsd curves decrease as expected for a p-type FET. As Vg is increased, the slopes of the individual I-Vsd curves decrease as expected for a p-type FET.

10. Measurement Plots of the conductance versus Vg. Vsd is 1V Plots of the conductance versus Vg. Vsd is 1V The transconductance of this device is 750 nS The transconductance of this device is 750 nS This value is within a factor of 2 of that recently reported for core/shell nanowire devices that were fabricated on conventional singlecrystal Si/SiO2 substrates. This value is within a factor of 2 of that recently reported for core/shell nanowire devices that were fabricated on conventional singlecrystal Si/SiO2 substrates. The device performance could be improved by decreasing the dopant concentration and/or minimizing trap states in the dielectric The device performance could be improved by decreasing the dopant concentration and/or minimizing trap states in the dielectric

11. Summary This paper has demonstrated NIL of nanometer through millimeter-scale features on flexible plastic substrates over large areas at room temperature. This paper has demonstrated NIL of nanometer through millimeter-scale features on flexible plastic substrates over large areas at room temperature. The ambient temperature NIL patterning technique has been shown to produce uniform features in a parallel and repeatable manner The ambient temperature NIL patterning technique has been shown to produce uniform features in a parallel and repeatable manner Moreover, NIL has been combined with bottom up assembly to fabricate SiNW FETs on flexible plastic substrates with device performances similar to nanowire FETs fabricated on conventional single-crystal substrates. Moreover, NIL has been combined with bottom up assembly to fabricate SiNW FETs on flexible plastic substrates with device performances similar to nanowire FETs fabricated on conventional single-crystal substrates. The development of simple and reproducible high-resolution patterning of plastics using NIL combined with the versatile function of nanowire building blocks could open up exciting opportunities over many length scales for plastic electronics and photonics. The development of simple and reproducible high-resolution patterning of plastics using NIL combined with the versatile function of nanowire building blocks could open up exciting opportunities over many length scales for plastic electronics and photonics.