1. CMM++ activities at MSU Y. Ermoline et al. Level-1 Calorimeter Trigger Joint Meeting, CERN, 13 – 17 September 2010

2. 1/6 CMM++ status, plans and schedule n2010: Technical specification and preliminary design review n CMM++ "real estate" (FPGA and links) and connectivity n Input for the schematic capture and VHDL/FW framework nLast version of the CMM++ document n combined information from different papers and emails in one note n Not yet the CMM++ specification - rather a working document nInterfaces feasibility study n 160 Mb/s CMM++ interface to CPM/JEM modules nTest stand at MSU n Understanding of the current L1Calo trigger system

3. 2/6 BLT FW modification for the data transfer tests (1) nTest the implementation of the 160 Mb/s CMM++ interface to CPM/JEM modules follow Richard’s proposal (clock/parity encoding/decoding) n tests at CERN (JEM) and CERN or Birmingham (CPM) n BLT from Mainz as a data sink nJEM-BLT at CERN (first week of July) n BLT and JEM module installed in the CERN test rig n BLT FW of last year re-compiled on Xilinx ISE 12.1 n JEM modified to Richards clock/parity scheme (clock line); the sum FPGA control register can control the operation: ð000 default mode 40 Mb/s ð001 160Mb/s with 80 MHz DDR clock on bit 0 (inverted words) ð010 Richards embedded clock/parity on bit 0 ð011 same on bit 24 ð100 sequence test on data bits 8,9,10,11

4. 3/6 BLT FW modification for the data transfer tests (2) nTest bench for the modified BLT FW (generates Richard’s format) n four 24-bit data words ðdefined in the VHDL file or loaded from input text file n odd parity is calculated for 96 bits and generates the clock/parity format n four words (24-bit data + clock/parity bit) are sent out at 160 MHz nFW modification were done to the Mainz BLT VHDL code: n only part of code for module “0” modified (slot N4 in the crate) n clock/parity bit is fed via BUFG into PLL and 80 MHz output clock is generated and fed into regional clock buffer BUFR n input data are phase corrected in IODELAY with IDELAYCTRL and recovered in IDDR using 80 MHz regional clock n data and clock/parity bit are sampled at 80 MHz and aligned in one word at 40 MHz n parity is calculated for 97 bits and error counter incremented on error n VME control of the BLT remain unchanged (IO delay control and error counters)

5. 4/6 BLT FW modification for the data transfer tests (3) nRun VHDL code trough synthesis and implementation n 1 timing constrain (related to PLL 80 MHz clock) is not met n project at: http://ermoline.web.cern.ch/ermoline/BLT/Firmware/blt.zip nNext steps: n add a VME control to the test bench n limited test (BLT in crate slot 3 + JEM in crate slot 4) in the CERN test rig using rudimentary VME commands n some more complete test with Mainz colleagues at CERN (?) n discuss on how to proceed with the CPM tests

6. 5/6 MSU test stand proposal and status (1) nMSU is going to develop and build the CMM++ module nThe test rig will be required: n acquire initial knowledge on CMM module operation n develop and test the CMM++ nSimilar to existing test rigs nInitially assembled at CERN, tested and then sent to MSU n Hardware (without DCS) n Online software n Online simulation nHardware list prepared n Some parts available or ordered n L1Calo modules - ? Proposed MSU test stand CPM/Jem and TTC crates at CERN

7. 6/6 MSU test stand proposal and status (2)