2. ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices Adders,subtractors, ALUs

3. Prev… XOR (2-level, 3-level) Equivalent symbols XNOR Parity Circuits (Odd, even) Daisy chain Tree Comparators Iterative Parallel

4. ECE311 Ch5 3 Adders/Subtractors Half Adder Full Adder Ripple Adder Full Subtractor Ripple Subtractor Adder/Subtractor Circuit

5. ECE311 Ch5 4 Half Adder: adds two 1-bit operands Truth table : X Y HS=(X+Y) CO 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Y X H S CO

6. Full Adders: provide for carries between bit positions Basic building block is “full adder” 1-bit-wide adder, produces sum and carry outputs Truth table: XYCinSCout 00000 00110 01010 01101 10010 10101 11001 11111 S is 1 if an odd number of inputs are 1. COUT is 1 if two or more of the inputs are 1. Recall: Table 2-3, pp32

7. Full-adder circuit

8. Ripple adder Speed limited by carry chain Faster adders eliminate or limit carry chain 2-level AND-OR logic ==> 2 n product terms 3 or 4 levels of logic, carry lookahead

9. 74x283 4-bit adder Uses carry lookahead internally

10. 16-bit group- ripple adder

11. Subtraction Subtraction is the same as addition of the two’s complement. The two’s complement is the bit-by-bit complement plus 1. Therefore, X – Y = X + Y’ + 1

12. Full subtractor = full adder, almost X,Y are n-bit unsigned binary numbers Addition : S = X + Y Subtraction : D = X - Y = X + (-Y) = = X+ (Two’s Complement of Y) = X+ (One’s Complement of Y) + 1 = X+ Y’+ 1

13. ECE311 Ch5 12 Using Adder as a Subtractor Ripple Adder can be used as a subtractor by inverting Y and setting the initial carry ( CIN ) to 1

14. ECE311 Ch5 13 MSI Arithmetic Logic Units (ALU ) ALU performs Aithmetic and Logical Functions - A, B : 4 bits inputs - S3,S2,S1,S0 : Function select - M=0 : Arithmetic operations +=Plus, - = Minus M=1 : Logical operations : += OR,. =AND Example : Inputs Functions S3 S2 S1 S0 M=0 M=1 0 0 0 0 F= A-1+CIN F=A’ 0 1 1 0 F= A-B-1+CIN F=A XOR B’ 1 0 0 1 F= A+B+CIN F=A XOR B 1 0 1 1 F=(A OR B)+ CIN F=A+B 1 1 0 0 F= A+A+CIN F= 0000 1 1 1 1 F=A+CIN F=A S1 S2 S3 F1 F2 M CIN A0 S0 F0 B0 74x181 F3 COUT A1 B1 A2 B2 A3 B3 A=B P G

15. ECE311 Ch5 14 Chapter Summary Documentation Standards: - Gate symbols, Signals Active Levels, Bubble to Bubble Logic - Block diagram, Schematic Diagram, Timing Diagram. Combinational Logic design Structures: 1-Decoders : Binary Decoders, Cascading decoders, Implementing Logic Functions, Seven-Segment Decoders (HW5.18). 2-Encoders : Binary Encoder, Priority Encoder, Cascading Encoders, Encoder applications. 3-Three State Buffers : SSI buffers, MSI Octal Buffer, Octal Three-state Transceiver

16. 15 Chapter Summary 4- Multiplexers : MUX operation, Single/Multiple outputs MUX, Expanding MUXs 5- Demultiplexers : MUX/DMUX operation, Using Decoders as Demultiplexers. 6- XOR and XNOR Gates: Logic Symbols, Equivalent Symbols, Parity Circuits using XOR gate, Parity Circuit application ( memory unit checking ) 7- Comparators : Parallel Comparators, Iterative Comparators, Cascading Comparators 8-Adders : Half Adder, Full Adder, Ripple Adder, Subtractor, Ripple Adder / Subtractor Unit,Group-Ripple Adder 9- Arithmetic Logic Units

17. Next… HW#11: Assign Mon. 11/10/2003 Work Wakerly problems 5.22, 5.54, 5.57(a,b,c), 5.68 Due: Wed. 11/19/2003 Combinational circuits Design examples Reading Wakerly CH-6.1-6.2