1. LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V blo c k I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell FPGA - Field Programmable Gate Array

2. The structure of FPGA

3. LB Symmetrical Array LB Row-based LB Sea-of-Gates LB Hierarchical (CPLD) PLA Architecture of FPGA-s

4. 0 1 1 1 1 1 1 1 X 3 X 2 X 1 Y 1 Y X 3 X 2 X 1 Example: realisation of the OR function based on LUT

5. LUT S MUX 0 1 S 0 1 T T Logical block based on LUT-s

6. S 0 1 MUX S 0 1 S 0 1 0 0 1 1 X1X1 X2X2 X3X3 X2X2 X3X3 Y Y = X 1 X 2 + X 1 X 3 X 1 X 2 + X 1 X 3 X3X3 X2 X2 1001 X 1 = 0X 1 = 1 X 3 = 0 X 3 = 1X 2 = 0 X 2 = 1 Example: realisation of function based on MUX-s.

7. LB CLK SBCB Connection arrays Long lines Connections between the neighbours Interconnection resources FPGA Symmetrical FPGA

8. LB Row of interconnection resources in a FPGA with architecture LB Long lines over logical blocks For example, Actel-i Act-1, Act-2 FPGA-d

9. Interconnection resources in Sea-of-Gates type FPGA Cell Neighbouring connectionsConnections in 4x4 blocks Cell Connections in 16x16 blocks 4x4 cell Connections in the array I/O blocks I/O b l o c k s I/O b l o c k s 16x16 For example. XILINX XC6200 and ACTEL-i ES serial arrays

10. Interconnection resources in CPLD type FPGA PLA Local connection resource PLA I/O blocks Local connection resources Local connection resource Global connection resource Logical block Macrocell

11. T T S/V contact I/O pad S MUX 0 1 S 0 1 I/O cells

12. . Description of the hardware. (Boolean functions Logical circuit, VHDL …) Logical optimization / minimisation Programming / Configuring Technology Mapping Placement Routing Designing of hardware based on FGPA