1. Instruction Set Architectures

2. Our Progress Done with levels 0 and 1 Seen multiple examples of level 2 Ready for ISA general principles

3. Choices, choices ISA design is a balancing act – Hardware complexity – Compiler complexity – Programmer friendliness – Backwards compatibility

4. Choice 0 : Instruction Length Will instructions be – Fixed length ARM Easier to decode – Variable length Intel Better use of space

5. Choice 1 : Memory Model Memory Model – Is the machine little endian or big endian?

6. Choice 1 : Memory Model Memory Model – Is the machine little endian or big endian? "Compute" Which is easier for programmers to read? Little Endian+3+2+1+0 0000pmoC 0004\0etu Big Endian+0+0+1+2+3 0000Comp 0004ute\0

7. Choice 1 : Memory Model Memory Model – Is the machine little endian or big endian? -16 (FFFFFFF0) followed by 5 (00000005) Which is easier to convert int to char? Little Endian+3+2+1+0 0000FF F0 000400 05 Big Endian+0+0+1+2+3 0000FF F0 000400 05

8. Who uses what? MARS is little endian – MIPS hardware is biendian

9. Choice 2 : CPU Storage How will CPU store data? – General Purpose vs Special Purpose Registers – How many?

10. Choice 2 : CPU Storage Accumulator architecture – Single Result Register – Shorter instructions Add X vs Add $9, $8, $7 – More fiddly to program

11. Choice 2 : CPU Storage General Purpose Registers – Any data (mostly) anywere – ARM style – More flexible/easier to program

12. Choice 2 : CPU Storage Special Purpose Registers – Intel: Some instructions must work with specific registers – Motorola: Separate data/address registers

13. Choice 2 : CPU Storage How many? – Fewer = more data shuffling – More = More hardware More bits eaten up in instructions – 8 registers = 3 bits – 16 registers = 4 bits – 32 regisers = 5 bits

14. Choice 3 : Addressing Modes How restricted are we to registers? Memory-Memory – Can work directly with memory in all instructions – Memory Address are BIG!!! Register-Memory (Intel) – At least one operand in register, other can be directly from memory Load-Store (ARM) – Only special load/store instructions can reference memory More Flexible More Complex

15. Choice 3 : Addressing Modes How can we address memory: – Directly MOV eax, [0x1040] – Indirectly LDR r0, [r1] 0x1040

16. Choice 4 : What Operations Lots of different instructions/formats? – CISC – More hardware – Shorter programs – Longer opcodes Fewer machine instructions – RISC 500 instructions * 4 addressing modes = 2000 instructions = 11 bit opcodes 100 instructions * 2 addressing modes = 200 instructions = 8 bit opcodes

17. Choice 3 : Number of Operands How many operands? – 0 : ADD Stack based operations – 1 : ADD 100 LMC – 2 : Add r2, r3 Intel – 3 : Add r2, r3, r4 Longer, More flexible Instructions

18. Examples 3 Operand Instructions: Z = X  Y + W  U LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R1,R2 MULT R3,R3,R4 ADD R1,R1,R3 STORE Z, R1 R1X R2Y R3W R4U

19. Examples 3 Operand Instructions: Z = X  Y + W  U LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R1,R2 MULT R3,R3,R4 ADD R1,R1,R3 STORE Z, R1 R1XY R2Y R3W R4U

20. Examples 3 Operand Instructions: Z = X  Y + W  U LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R1,R2 MULT R3,R3,R4 ADD R1,R1,R3 STORE Z, R1 R1XY R2Y R3WU R4U

21. Examples 3 Operand Instructions: Z = X  Y + W  U LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R1,R2 MULT R3,R3,R4 ADD R1,R1,R3 STORE Z, R1 R1XY + WU R2Y R3WU R4U

22. Examples 3 Operand Instructions: Z = X  Y + W  U LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R1,R2 MULT R3,R3,R4 ADD R1,R1,R3 STORE Z, R1 R1XY + WU R2Y R3WU R4U

23. 2 Operand 2 Operand Instructions – First operand is source and destination ADD r1, r2 r1 = r1 + r2 – Intel style:

24. Examples 2 Operand Instructions: Z = X  Y + W  U LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R2 MULT R3,R4 ADD R1,R3 STORE Z, R1 R1X R2Y R3W R4U

25. Examples 2 Operand Instructions: Z = X  Y + W  U LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R2 MULT R3,R4 ADD R1,R3 STORE Z, R1 R1XY R2Y R3W R4U Destination always same as first operand

26. Examples 2 Operand Instructions: Z = X  Y + W  U LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R2 MULT R3,R4 ADD R1,R3 STORE Z, R1 R1XY R2Y R3WU R4U

27. Examples 2 Operand Instructions: Z = X  Y + W  U LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R2 MULT R3,R4 ADD R1,R3 STORE Z, R1 R1XY + WU R2Y R3WU R4U

28. Examples 2 Operand Instructions: Z = X  Y + W  U LOAD R1,X LOAD R2,Y LOAD R3,W LOAD R4,U MULT R1,R2 MULT R3,R4 ADD R1,R3 STORE Z, R1 R1XY + WU R2Y R3WU R4U

29. Examples 1 Operand Instructions - Accumulator Z = X  Y + W  U LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z ACX Destination assumed to be accumulator

30. Examples 1 Operand Instructions - Accumulator Z = X  Y + W  U LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z ACX*Y Destination assumed to be accumulator

31. Examples 1 Operand Instructions - Accumulator Z = X  Y + W  U LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z ACX*Y tempX*Y

32. Examples 1 Operand Instructions - Accumulator Z = X  Y + W  U LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z ACW tempX*Y

33. Examples 1 Operand Instructions - Accumulator Z = X  Y + W  U LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z ACW*U tempX*Y

34. Examples 1 Operand Instructions - Accumulator Z = X  Y + W  U LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z ACW*U + X*Y tempX*Y

35. Examples 1 Operand Instructions - Accumulator Z = X  Y + W  U LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z ACW*U + X*Y tempX*Y 7 trips to main memory!!!

36. Stack Based Stack based CPU storage – Loads place value on stack – Math operations pop top two values, work with them, push answer – Store pops value off stack

37. Choice 2 : CPU Storage Java bytecode is stack based language: Pro/Con + Instruction Size + Hardware neutrality - Does not take advantage of complex hardwar - Lots of memory access

38. Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z X Destination assumed to be top of stack

39. Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z Y X Destination assumed to be top of stack

40. Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z X * Y Take off top two items, multiply, put result back on stack

41. Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z W X * Y

42. Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z U W X * Y

43. Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z W * U X * Y Take off top two items, multiply, put result back on stack

44. Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z W * U + X * Y Take off top two items, add, put result back on stack

45. Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z 11-14 trips to main memory (Mult/Add 2 or 3 each!)