1. DIGITAL 2 EKT 221 Date : Lecture : 2 hrs

2. Today’s Outline:  Multi-Level Combinational Logic  Lab1 – Overview (refer to Altera UP2 Manual)

3. Multilevel Comb. Logic  Notes Notes

4. LAB1 : ALTERA UP2 TRAINING BOARD

5. EEPROM Technology CPLD MAX7000S 2,500 logic gates SRAM Technology FLEX10K FPGA 70,000 logic gates

6. Push Buttons Switches 7 Segment Display Expansion Slot LED’s JTAG Jumpers Setting EPC1 – for non-volatile memory

7. UP2 Education Kit : User Guide  30 pages of specification for Altera UP2 board  It explains about the pin configuration for MAX and FLEX  JTAG Jumper setting  Expansion Slots  (Go Through the UP2 User Guide with students – comprehensively) – all students must have one copy each

8. Ensure that:  Functional SNF Extractor -> Timing SNF Extractor  The right Device is chosen -> FLEX – EPF10K70RC240-4  The right pin configuration is done, refer to UP2 user guide  The right file is used. (set project as current file)  The right format file is loaded (*.sof or *.pof)  SOF – for SRAM Object File (FLEX)  POF – for Programmer Object File (MAX)