1. Retiming EECS 290A Sequential Logic Synthesis and Verification

2. Outline  Motivation  Graphs  Classical approach to retiming  Improved approach using clock skew

3. Motivation  Retiming can reduce the clock cycle of the circuit Critical path has delay 4All paths have delay 2

4. Directed Graphs  Graph is set of vertices and edges G = (V,E)  Each edge is directed (has a source and a sink)  A path is the sequence of vertices connected by edges  A cycle is the circular path  Graph is strongly connected if there exist a path from any vertex to any other vertex.  For the general formulation of the graph problems, each edge e has distance, d(e), and a latency, t(e)  In this lecture (on retiming) Graph is the sequential netlist Graph is the sequential netlist Vertices are combinational nodesVertices are combinational nodes Edges are wiresEdges are wires Vertices have combinational delay Vertices have combinational delay Latency of an edge is the number of latches on the edge Latency of an edge is the number of latches on the edge

5. Classical Formulation  During retiming the registers are moved over combinational nodes: w r (e u  v ) = r(v) + w(e u  v ) – r(u), where r(v) are the registers moved from the outputs to the inputs of v.  For each path p: u  v we define its weight w(p) as the sum total of registers on all edges.  The minimum clock period stands for the maximum 0-weight path P = max  p: w(p) = 0 {d(p)}  Matrices W(u,v) and D(u,v) are defined for all pairs of vertices that are connected by a path that does not go through the host node W(u,v) = min  p: u  v {w(p)} and D(u,v) = max  p: u  v and w(p)= W(u,v) {d(p)} C. E. Leiserson and J. B. Saxe. Retiming synchronous circuitry, Algorithmica, 1991, vol. 6, pp. 5-35.

6. Classical Formulation (cont.)  W(u,v) denotes the minimum latency, in clock cycles, for the data flowing from u to v  D(u,v) gives the maximum delay from u to v over all path with the minimum latency  The computation of retiming labels for the clock period P is performed by solving a Linear Programming problem: r(u) – r(v)  w(e u  v ),  e u  v  E r(u) – r(v)  W(u,v) – 1,  D(u,v) > P  The constraints ensure that after retiming the latency of each edge is non-negative the latency of each edge is non-negative each path whose delay is larger than the clock period has at least one register on it each path whose delay is larger than the clock period has at least one register on it

7. Theorem  Theorem. Let G = (V,E,d,t) be a synchronous circuit with maximum mean cycle ratio R(C*(G)), and let  min (G) be the minimum clock period obtained by retiming G. Then  R(C*(G))    min (G)   R(C*(G))  +d max -1  R(C*(G))    min (G)   R(C*(G))  +d max -1 where d max = max{ d(v) : v  V }. where d max = max{ d(v) : v  V }. M. C. Papaefthymiou, “Understanding retiming through maximum average-delay cycles”, Mathematical Systems Theory 27(1), 1994, pp. 65-84.

8. The Initial State Problem  In some cases, for backward retiming, the initial state cannot be computed a+b 0 0 0 0  1 0 ? ? 

9. Solution to Initial State Problem  Additional hardware: multiplexers and a reset signal  Reset is 1 at the first clock, and 0 afterwards a+b 1 0 1 0 Reset 0 1 0 1 a+b Reset Detach initial values from latches Propagate constants in MUXes

10. Implementation of Retiming  Leiserson/Saxe compute the matrices, generate constraints, and then solve the LP problem  Shenoy/Rudell compute the matrix one column at a time Reduced space requirements, still prohibitive runtime Reduced space requirements, still prohibitive runtime  Sapatnekar proposed a way of utilizing retiming/skew equivalence to reduce the number of constraints generated S. S. Sapatnekar, R. B. Deokar, “Utilizing the retiming-skew equivalence in a practical algorithms for retiming large circuits”, IEEE Trans. CAD, vol. 15(10), Oct.1996, pp. 1237-1248.

11. Sapatenekar’s Retiming Algorithm  Find ASAP and ALAP skews for a feasible clock period Use binary search to find a feasible clock period Use binary search to find a feasible clock period  Perform min-delay retiming by moving latched to fit the timing window  Perform min-area retiming under delay constraints by solving a reduced LP problem The reduced set of constraints is generated using the skews The reduced set of constraints is generated using the skews The LP problem is solved efficiently using a variation of network simplex method The LP problem is solved efficiently using a variation of network simplex method  Improvement: Start by finding maximum ration using Howard’s algorithm

12. Example PI PO Clock period = 3 Buffer delay = 1 Initial ALAP ASAP ALAP skew = -1 ASAP skew = -3 PI PO PI PO Bounds on how far latches can move