1. ECE- 1551 DIGITAL LOGIC LECTURE 11: STANDARD CIRCUITS Assistant Prof. Fareena Saqib Florida Institute of Technology Fall 2015, 09/24/2015

2. Recap  Don’t Care Conditons  Karnaugh map of Product of Maxterms  Exclusive OR Function  Code Convertors  Excess 3

3. Agenda  Code Convertors  BCD to Gray Code  Parity Generator  BCD to 7 segment display decoder

4. Design Code Converters  Binary codes and how to develop code converters.  An n-bit binary code is a group of n bits that assumes up to 2^n distinct combinations of 1’s and 0’s. With each combination representing one element o the set that is being coded Combinational Logic IN OUT

5. Binary Codes  BCD, Binary representation of decimal numbers.  Excess 3  Gray Code  ASCII

6. Gray Code- Specification  Specification: Excess ‐ 3 is an unweighted code in which each coded combination is obtained from the corresponding binary value plus 3.  Application:its selfcomplementing property. Example 9’s complement of 3 is 6 and 6 9’s complement is 3.  Excess 3 representation of 3 is 0110 and of 6 is 1001  9’s complement of 3 only requires flipping the bits from 1 to 0 and 0 to 1 (as we did in 1’s complement).  Its not true in BCD where 3 is 0011 and 6 is 0110. We cannot directly calculate the 9’s complement.

7. Gray Code: Specification to truth table b3b2b1b0e3e2e1E0 00000000 00010001 00100011 00110010 01000110 01010111 01100101 01110100 10001100 10011101 10101111 10111110 11001010 11011011 11101001 11111000

8. Gray Code:– Minimization using K-maps cd b1b0b1b0 00 01 11 10 00 01 11 10 g 0 = b 0 ’ b3b2b3b2 00 01 11 10 00 01 11 10 g 1 = (b 1 xor b 0 )’ 00 01 11 10 00 01 11 10 g 2 = b 2 ’b 1 +b 2 b 1 ’b 0 00 01 11 10 00 01 11 10 g 3 = b 3 +b 2 b 0 +b 2 b 1 b1b0b1b0 b3b2b3b2 b1b0b1b0 b3b2b3b2 b1b0b1b0 b3b2b3b2 g0g0 g1g1 g2g2 g3g3

9. Application 2: Parity Generator b3b2b1b0P0 00000 00011 00101 00110 01001 01010 01100 01111 10001 10010 10100 10111 11000 11011 11101 11110

10. Parity Generator : K-maps 0101 1010 011 1010 cd b1b0b1b0 00 01 11 10 00 01 11 10 P 0 = ?? b3b2b3b2 P0P0

11. Parity Generator  Design circuit.  Discussed in class

12. BCD to 7 segment display decoder b3b2b1b0abcdefg 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

13. Parity Generator : K-maps 111 11 XXXX 11XX cd b1b0b1b0 00 01 11 10 00 01 11 10 a= ?? b3b2b3b2 a XXXX XX cd b1b0b1b0 00 01 11 10 00 01 11 10 b= ?? b3b2b3b2 b XXXX XX cd b1b0b1b0 00 01 11 10 00 01 11 10 c= ?? c b3b2b3b2 XXXX XX cd b1b0b1b0 00 01 11 10 00 01 11 10 d= ?? d b3b2b3b2

14. Parity Generator : K-maps 1111 0111 XXXX 11XX cd b1b0b1b0 00 01 11 10 00 01 11 10 e= ?? b3b2b3b2 e XXXX XX cd b1b0b1b0 00 01 11 10 00 01 11 10 f= ?? b3b2b3b2 f 0011 1001 XXXX 11XX cd b1b0b1b0 00 01 11 10 00 01 11 10 g= ?? g b3b2b3b2