1. EE141 Manufacturing 1 Chapter 2 Manufacturing Process and CMOS Circuit Layout 1 st rev. : March 7, 2003 2 nd rev. : April 10, 2003

2. EE141 Manufacturing 2 CMOS Process

3. EE141 Manufacturing 3 A Modern CMOS Process Dual-Well Trench-Isolated CMOS Process

4. EE141 Manufacturing 4 The Manufacturing Process For a great tour through the IC manufacturing process and its different steps, check www.fullman.com/semiconductors/semiconductors.html

5. EE141 Manufacturing 5 Patterning of SiO2 Si-substrate (a) Silicon base material (b) After oxidation and deposition of negative photoresist (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist SiO 2 Si-substrate SiO 2 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching (f) Final result after removal of resist Hardened resist Chemical or plasma etch

6. EE141 Manufacturing 6 oxidation optical mask process step photoresist coatingphotoresist removal (ashing) spin, rinse, dry acid etch photoresist stepper exposure development Typical operations in a single photolithographic cycle (from [Fullman]). Photo-Lithographic Process

7. EE141 Manufacturing 7 Recurring Process Steps  Diffusion and Ion Implantation: change dopant concentration of some parts of the material.  Deposition: Silicon Nitride S i3 N 4 (CVD, chemical vapor deposition, Polysilicon (polycrystalline silicon), Aluminum  Etching: Si 2 O (acid), Plasma etching (dry etching)  Planarization: Chemical-mechanical planarization (CMP) on top of Si 2 O before deposition of an extra metal layer.

8. EE141 Manufacturing 8 CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers

9. EE141 Manufacturing 9 CMOS Process Walk-Through p + p-epi (a) Base material: p+ substrate with p-epi layer p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask p + p-epi SiO 2 3 SiN 4 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer)

10. EE141 Manufacturing 10 CMOS Process Walk-Through SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride (e) After n-well and V Tp adjust implants n (f) After p-well and V Tn adjust implants p

11. EE141 Manufacturing 11 CMOS Process Walk-Through (g) After polysilicon deposition and etch poly(silicon)

12. EE141 Manufacturing 12 CMOS Process Walk-Through

13. EE141 Manufacturing 13 Advanced Metallization

14. EE141 Manufacturing 14 Advanced Metallization

15. EE141 Manufacturing 15 Design Rules

16. EE141 Manufacturing 16 3D Perspective Polysilicon Aluminum

17. EE141 Manufacturing 17 Circuit Under Design

18. EE141 Manufacturing 18 Its Layout View

19. EE141 Manufacturing 19 CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) ColorRepresentation Yellow Green Red Blue Magenta Black Select (p+,n+) Green

20. EE141 Manufacturing 20 Layers in 0.25  m CMOS process

21. EE141 Manufacturing 21 CMOS Inverter Layout

22. EE141 Manufacturing 22 Sticks Diagram 1 3 In Out V DD GND Stick diagram of inverter Dimensionless layout entities Only topology is important Final layout generated by “compaction” program

23. EE141 Manufacturing 23 Design Rules  Interface between designer and process engineer  Guidelines for constructing process masks  Unit dimension: Minimum line width  scalable design rules: lambda parameter  absolute dimensions (micron rules)

24. EE141 Manufacturing 24 Intra-Layer Design Rules Metal2 4 3

25. EE141 Manufacturing 25 Transistor Rules (DRC)

26. EE141 Manufacturing 26 Vias and Contacts

27. EE141 Manufacturing 27 Select Layer

28. EE141 Manufacturing 28 Layout Editor (Cadence, Magic,..)

29. EE141 Manufacturing 29 Design Rule Checker (on-line check) poly_not_fet to all_diff minimum spacing = 0.14 um.

30. EE141 Manufacturing 30 CMOS Layout of Complexe Gate: From Chapter 6 Slides and Insert D Designing Combinational Logic Circuits March 28, 2003

31. EE141 Manufacturing 31 Example Gate: NAND

32. EE141 Manufacturing 32 Example Gate: NOR

33. EE141 Manufacturing 33 Complex CMOS Gate OUT = D + A (B + C) D A BC D A B C

34. EE141 Manufacturing 34 Constructing a Complex Gate OUT = D + A (B + C)

35. EE141 Manufacturing 35 Stick Diagrams Contains no dimensions Represents relative positions of transistors In Out V DD GND Inverter A Out V DD GND B NAND2

36. EE141 Manufacturing 36 Stick Diagrams C AB X = C (A + B) B A C i j j V DD X X i GND AB C PUN PDN A B C Logic Graph PUN: Pull-up Network, PDN: Pull-down Network

37. EE141 Manufacturing 37 Two Versions of C (A + B) X CABABC X V DD GND V DD GND Two Strips Line of DiffusionsOne Strip Line of Diffusions

38. EE141 Manufacturing 38 Consistent Euler Path (Insert D of textbook) j V DD X X i GND AB C ABC

39. EE141 Manufacturing 39 OAI22 Logic Graph C AB X = (A+B)(C+D) B A D V DD X X GND AB C PUN PDN C D D A B C D

40. EE141 Manufacturing 40 Example: x = ab+cd Euler Paths For both PUD and PDN

41. EE141 Manufacturing 41 Cell Design  Standard Cells (gate collection)  General purpose logic  Can be synthesized  Same height, varying width  Datapath Cells  For regular, structured designs (arithmetic)  Includes some wiring in the cell  Fixed height and width

42. EE141 Manufacturing 42 Standard Cell Layout Methodology – 1980s signals Routing channel V DD GND V DD

43. EE141 Manufacturing 43 Standard Cell Layout Methodology – 1990s M2 No Routing channels V DD GND M3 V DD GND Mirrored Cell

44. EE141 Manufacturing 44 Standard Cells Cell boundary N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” 2 Rails ~10 In Out V DD GND

45. EE141 Manufacturing 45 Standard Cells In Out V DD GND InOut V DD GND With silicided diffusion With minimal diffusion routing

46. EE141 Manufacturing 46 Standard Cells A Out V DD GND B 2-input NAND gate

47. EE141 Manufacturing 47 CMOS Fabrication and Layout See the supplement data in Web! http://access.ee.ntu.edu.tw