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EE 466/586 VLSI Design Partha Pande School of EECS Washington State University

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Presentation on theme: "EE 466/586 VLSI Design Partha Pande School of EECS Washington State University"— Presentation transcript:

1 EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

2 Lecture 2 The MOS Transistor (Reference: Chapter 2 of Weste and Harris or Chapter 2 of HJS)

3 The MOS Transistor Polysilicon Aluminum

4 Structural Details  Channel length L  Typical values of L today vary from 90nm to 32 nm  The dimension will continue to scale according to Moore’s law  Perpendicular to the plane of the figure is the channel width W  Much larger than the minimum length  Gate oxide thickness  Around 25 Å

5 Operational Mechanism  We consider a NMOS transistor  N+ source and N+ drain regions separated by p-type material  The body or substrate, is a single-crystal silicon wafer  Suppose, source, drain and body are all tied to ground and a positive voltage applied to the gate  A positive gate voltage will tend to draw electrons from the substrate into the channel region  A conducting path is created between drain and source  Current will flow from drain to source in presence of a voltage difference between the source and the drain  The gate voltage needed to initiate formation of a conducting channel is termed as the threshold voltage Vt

6 Threshold Voltage: Concept

7 The Threshold Voltage Follow board notes

8 What is a Transistor? A Switch! |V GS | An MOS Transistor

9 The Body Effect

10 Current-Voltage Relations  Follow board notes

11 Current-Voltage Relations Quadratic Relationship 00.511.522.5 0 1 2 3 4 5 6 x 10 -4 V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V ResistiveSaturation V DS = V GS - V T

12 Transistor in Linear

13 Transistor in Saturation Pinch-off

14 Current-Voltage Relations The Deep-Submicron Era  The quadratic model is valid for long channel devices  In DSM, channel length is scaled  Vertical and horizontal electric fields are large and they interact with each other  Saturation in DSM devices occur when the carriers reach velocity saturation

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16 Effect of high fields Horizontal Field Vertical Field

17 Effect of high fields (Cont’d)  Effect of the vertical field on the mobility  The vertical field increases the electron scattering at the surface of the channel  Follow board notes  The horizontal field acts to reduce the mobility even further

18 Velocity Saturation

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20 Velocity Saturation (Cont’d)

21 Current Equations

22 Current Equation (Cont’d)

23 Current Equation (Saturation)

24 Current-Voltage Relations The Deep-Submicron Era Linear Relationship -4 V DS (V) 00.511.522.5 0 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Early Saturation

25 Perspective I D Long-channel device Short-channel device V DS V DSAT V GS - V T V GS = V DD

26 I D versus V GS 00.511.522.5 0 1 2 3 4 5 6 x 10 -4 V GS (V) I D (A) 00.511.522.5 0 0.5 1 1.5 2 2.5 x 10 -4 V GS (V) I D (A) quadratic linear Long Channel Short Channel

27 I D versus V DS -4 V DS (V) 00.511.522.5 0 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V 00.511.522.5 0 1 2 3 4 5 6 x 10 -4 V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V ResistiveSaturation V DS = V GS - V T Long ChannelShort Channel

28 Simple Model versus SPICE V DS (V) I D (A) Velocity Saturated Linear Saturated V DSAT =V GT V DS =V DSAT V DS =V GT

29 A PMOS Transistor -2.5-2-1.5-0.50 -0.8 -0.6 -0.4 -0.2 0 x 10 -4 V DS (V) I D (A) Assume all variables negative! VGS = -1.0V VGS = -1.5V VGS = -2.0V VGS = -2.5V

30 Transistor Model for Manual Analysis

31 The Transistor as a Switch

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