1. POLITECNICO DI MILANO A SystemC-based methodology for the simulation of dynamically reconfigurable embedded systems Dynamic Reconfigurability in Embedded Systems Design Chiara Sandionigi: chiara.sandionigi@dresd.orgchiara.sandionigi@dresd.org Relatore: Prof. Donatella Sciuto Correlatore: Ing. Marco Domenico Santambrogio

2. 22 Basic concepts and Motivations Basic concepts Dynamically reconfigurable computing: the ability of altering a microarchitecture, once it has been deployed and during the execution of the system, to meet at the best the execution mode of object code Target device: FPGA Motivations Modeling and verification of dynamically reconfigurable embedded systems Definition of a validation phase representing a bridge between high level specification phase and low level implementation phase

3. 33 Goals Innovative contributions Definition and implementation of a methodology for the simulation of dynamically reconfigurable embedded systems System modeling Architecture validation Application verification Design space exploration Definition of the validation phase inside a complete design flow for dynamically reconfigurable embedded systems System management during simulation execution.:: No support in the state of the art ::.

4. 44 Outline SyCERS Modeling of reconfiguration Architecture Integration in Earendil Integration in ReSP Experimental results Setup and main results DES MD5 Canny Conclusions and future work

5. 55 SyCERS: Modeling of reconfiguration SyCERS: SystemC-based simulator for dynamically reconfigurable embedded systems Modeling of reconfiguration exploiting SystemC module’s structure sc_method/ sc_thread/ sc_cthread sc_module

6. 66 SyCERS: Architecture Dynamic loading of applications Applications running on processor of FPGA

7. 77 SyCERS: Integration in Earendil Definition of a phase for the validation of dynamically reconfigurable embedded systems Definition of a complete design flow

8. 88 SyCERS: Integration in ReSP Simulation platform built using Python, SystemC and C++ programming languages Aim: create mechanisms to connect and analyze SystemC components and to manage simulation Exploitation of ReSP reflective capabilities for system management during simulation execution introspection inside the components monitoring of the status of the components modification of the status of the components run-time composition of the architecture

9. 99 Experimental results: Setup and main results System setup Intel Core Duo 2 GHz processor, 1 GB memory and Mac OS X 10.5.5 operating system Apple GCC version 4.0.1 SystemC version 2.2 Case studies DES: parallelism exploitation for the exploration of solution space MD5: algorithm structure exploitation for the evaluation of reconfiguration time Canny: algorithm structure exploitation for the evaluation of dynamic reconfiguration

10. 10 Experimental results: DES Input parameters for DES applied to 1,28 kb file Memory size: 500 kB Memory reading time: 30 ns Memory writing time: 30 ns Reconfiguration time: 3 ms RFUOpsActivityT (ns) A20,3814020 B8110560 C81 D70,8989480 RFUOpsActivityT (ns) A20,1634020 B21124600 RFUOpsActivityT (ns) A20,2914020 B11113800 C11113800

11. 11 Experimental results: MD5 Input parameters for MD5 applied to 512-bit block Reconfiguration time: 2,932 ms OperationTime (ms) Reconfiguration A2,932 Elaboration A0,274 Reconfiguration B2,932 Elaboration B0,144 Reconfiguration C2,932 Elaboration C0,144 Reconfiguration D2,932 Elaboration D0,168 Reconfiguration E2,932 Elaboration E0,144 Total15,534 Reconfiguration T14,66 Elaboration T0,874

12. 12 Experimental results: Canny Input parameters for Canny applied to 16 kb file Memory size: 500 kB Memory reading time: 30 ns Memory writing time: 30 ns Reconfiguration time: 3 ms RFUOpsActivityT (ns) A8126700 RFUOpsActivityT (ns) A4113350 B41 RFUOpsActivityT (ns) A4111880 B20,6247410 C20,6247410

13. 13 Conclusions and future work Definition and implementation of a methodology for the simulation of dynamically reconfigurable embedded systems Definition of the validation phase inside a complete design flow for dynamically reconfigurable embedded systems System management during simulation execution Future work Add flexibility in terms of scheduling policies choice Take into account the problem of modules placement for dynamically reconfigurable systems based on FPGA

14. 14 Questions