1. Actel re-programming at CERN Actels on S9011AT, TPSFE and TBS boards have been re-programmed with new specifications / new implementations from Vladimir Koutsenko and myself at CERN For each board, new specifications from Alexei Lebedev will be shown and explained in this talk Lucio Accardo Tracker meeting – October the 17 th, 2005

2. S9011AT (1/2) WRITE REGISTERS Each LeCroy command will be formed by pairs of bits: “10” will generate a high level (‘1’) control bit, while “01” will generate a low level (‘0’) control bit. “10” pattern always means OFF, except for S9053B. Other pairs’ combinations will not affect control signals.

3. READ REGISTERS P : power on bit; it is ‘1’ at the power on, and it is autoclear when it is read S : status of the 3.3V Actel brother’s LR; ‘0’ is a good status T : trip of Actel brother’s status; ‘1’ is a trip occurred, it is autoclear C : shows command to 3.3V Actel brother’s LR; ‘0’ is LR ON TPSFE, TBS, TDR2 status: respectively DCDCS9051(B/A), DCDCS9055(B/A), DCDCS9053(B/A), status; ‘0’ is a good status TPSFE, TBS, TDR2 local control: respectively DCDCS9051(B/A), DCDCS9055(B/A), DCDCS9053(B/A), commands from Actel: ‘1’ is DCDC OFF (except S9053B, inverted) TPSFE, TBS, TDR2 global control: respectively DCDCS9051(B/A), DCDCS9055(B/A), DCDCS9053(B/A), signals to DCDCs; they are diode ORed of commands from Actels Trip: records changing from ‘0’ to ‘1’ of TPSFE, TBS, TDR2 status bits IMPROVEMENTS Protection for 3.3 V DCDC converters may be required (to avoid both halves ON). This has been implemented by myself on saturday, with a few lines modification in the actual VHDL code. S9011AT (2/2)

4. TPSFE (1/2)

5. WRITE REGISTERS Each LeCroy command will be formed by pairs of bits: “10” will generate a high level (‘1’) control bit, while “01” will generate a low level (‘0’) control bit. “10” pattern always means OFF, except for A. Other pairs’ combinations will not affect control signals A: when pair is “10” Automode is set ON and counters are cleared; when pair is “01” Automode is set OFF and counters are Autoclear; Actels’ trip counters are always Autoclear READ REGISTERS P, S, C: the same as in S9011AT A: means Automode ON if ‘1’, Automode OFF if ‘0’; default value is ‘1’ Status, local control, global control: the same as in S9011AT Counters: record changes from ‘0’ to ‘1’ of LRS, LRK, TDR (LR) status bits, up to 15 IMPROVEMENTS No improvements are needed in the Actels’ VHDL code To be investigated why status bits from TDR2 are high when 3.3V LRs are working fine, maybe changes of some resistors are needed TPSFE (2/2)

6. TBS (1/2) Each LeCroy command will be formed by pairs of bits: “10” will generate a high level (‘1’) control bit, while “01” will generate a low level (‘0’) control bit. Other pairs’ combinations will not affect control signals.

7. WRITE REGISTERS LR: on each TBS there are 4 LRs, 2 active, with cold redundancy; each LR supplies 6 ladders. There is an automatic switch to cold LR, activated from a voltage comparator. It is possible to switch ON (“01”) and OFF (“10”) each LR 60/80: it is possible to set 80V or 60V for each LR; “10” generates a high level ‘1’ and sets 60V; default value is ‘0’, 80V READ REGISTERS P, S, T, C: the same as in S9011AT and TPSFE Local control, global control: the same as in S9011AT and TPSFE LR: indicates a switch to cold LR (‘1’). Default value is ‘0’ ADC bias voltage: V = 2.5V/4096 * ADC_value * 37.5 ADC current value: I = (2.073V – (2.5V/4096 * ADC_value)) * 119uA/V Current readout should be calibrated for each channel IMPROVEMENTS No improvements are needed in the Actels’ VHDL code TBS (2/2)

8. Conclusions Visit to CERN has been useful for understanding and de-bugging new specifications and implementations New specifications are different from the old ones, essentially in commands: now pairs of bits are used instead of single ones Collaboration with Vladimir Koutsenko has been also good and the support of both of us was useful to arrive to a final version of the Actels