1. 8085 interrupts

2. 8085 Interrupts Maskable –INTR –RST vectored Non-Maskable –TRAP Vectored –RST5.5, RST6.5, RST7.5, TRAP

3. Interrupt process enable by writing EI. mp checks INTR line at each instruction. if INTR is high, mp completes the current instr, disables Interrupt Flip-flop, sends INTA signal. An RST instru is inserted by INTA through external hardware. Mp saves the memory address of the next instru into stack. Program control is transferred to CALL location. The service routine starts at CALL location. At the end of the subroutine Int Flag is enabled again by EI instru. The last instr of the subroutine is RET to trasfer back the prog control to its orginal address.

4. RST instructions 8 RST instructions Mnemon ics Binary codeHexCall Lo cat ion D7D6D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 RST011000111C70000 RST111001111CF0008 RST211010111D70010 RST311011111DF0018 RST411100111E70020 RST511101111EF0028 RST611110111F70030 RST711111111FF0038 +5v Enable 1 1 1 1 1 0 1 1 EF to data bus

5. LXI SP, XX99H EI MVI A, 00H NXTCNT: OUT PORT1 MVI C, 01H CALL DELAY INR A JMP NXTCNT XX70: SERV:PUSH B PUSH PSW MVI B, 0AH MVI A, 00H FLASH:OUT PORT1 MVI C, 01H CALL DELAY CMA DCR B JNZ FLASH POP PSW POP B EI RET Main program Service routine Interrupt instr: EF At 0028H JMP xx70H Write a program to count continuously in binary with one second delay between each Count. Service routine at XX70H to flush FFH five times when the interrrupt occurs with some appropriate delay between flash

6. Issues in implementing interrupts Is there a minimum pulse width required for the INTR signals? –MP checks INTR, one clk period before the last-T state of an instruction cycle, therefore, the INTR pulse should be high at least for 17.5 T-states. How long can the INTR pulse stay high? Can the MP be interrupted again before the completion of the first interrupt service routine?