1. FPGA Ethernetlink to DAQ level translation SMA/ LEMO RJ45 TLU Virtex 6 6 HDMI fanout HDMI OUT e.g. DCC-fanout HDMI IN Xilinx ML605-Board global clock trigger diff local clock

2. FPGA MUX clocks clk fanout trigger fanout trigger etc. algorithms/ combinatorial local clock to HDMI 1 from HDMI bussy

4. FPGA MUX clocks clk fanout trigger fanout trigger etc. algorithms/ combinatorial local clock to HDMI 1 from HDMI bussy

5. level trans- lation SMA LEMO 8 HDMI fanout HDMI IN global clock trigger local clock CPLD combinatorial MUX