1. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Topics n FPGA fabric architecture concepts.

2. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Introduction n The basic structure of FPGAs known as fabrics. n There are several different ways to build an FPGA. n Two major styles of FPGA are: (i) SRAM Based FPGAs (ii) Antifuse Programmed FPGAs

3. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Elements of an FPGA fabric Three major types of elements in FPGA are: n Combinational Logic. n Interconnect. n I/O pins. … LE interconnect IOB …

4. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Terminology n Configuration: bits that determine logic function + interconnect. n CLB: combinational logic block = logic element (LE). n LUT: Lookup table = SRAM used for truth table. n I/O block (IOB): I/O pin + associated logic and electronics.

5. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Logic element n Programmable: –Input connections. –Internal function. n Coarser-grained than logic gates. –Typically 4 inputs. n Generally includes register. n May provide specialized logic. –Adder carry chain.

6. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Example logic element n Lookup table: about 00 01 10 11 memory a b out 00100010 0 0 1 0 10011001 1 0 0 1

7. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Logic synthesis n How do we break the function into logic elements? n How do we implement an operation within a logic element?

8. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Placement n Where do we put each piece of logic in the array of logic elements? … LE

9. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Programmable wiring n Organized into channels. –Many wires per channel. n Connections between wires made at programmable interconnection points. n Must choose: –Channels from source to destination. –Wires within the channels.

10. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Programmable interconnection point DQ

11. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Programmable wiring paths

12. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Choosing a path LE

13. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Routing problems n Global routing: –Which combination of channels? n Local routing: –Which wire in each channel? n Routing metrics: –Net length. –Delay.

14. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Segmented wiring Length 1 Length 2

15. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Offset segments

16. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR I/O n Fundamental selection: input, output, three- state? n Additional features: –Register. –Voltage levels. –Slew rate.

17. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Programming technologies n SRAM. –Can be programmed many times. –Must be programmed at power-up. n Antifuse. –Programmed once. n Flash. –Similar to SRAM but using flash memory.

18. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Programmable switch technology Anti-fuse Flash SRAM Switch by default is OFF; when programmed it is ON. Advantages: negligible delay small area overhead Disadvantages: not really reconfigurable; one time programmable Switch by default is ON; when programmed it is OFF. Advantages: programming not lost when device is turned off. Disadvantages: requires more manufacturing steps SRAM bit cell stores the programmability of the device Advantages: can be reconfigured quickly and as repeatedly as required no special fabrication steps Disadvantages: takes more area loses charge when turned off

19. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Configuration n Must set control bits for: –LE. –Interconnect. –I/O blocks. n Usually configured off-line. –Separate burn-in step (antifuse). –At power-up (SRAM).

20. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Configuration vs. programming n FPGA configuration: –Bits stay at the device they program. –A configuration bit controls a switch or a logic bit. n CPU programming: –Instructions are fetched from a memory. –Instructions select complex operations. CPUmemory add r1, r2IRadd r1, r2

21. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Reconfiguration n Some FPGAs are designed for fast configuration. –A few clock cycles, not thousands of clock cycles. n Allows hardware to be changed on-the-fly.

22. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR FPGA fabric architecture questions n Given limited area budget: –How many logic elements? –How much interconnect? –How many I/O blocks?

23. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Logic element questions n How many inputs? n How many functions? –All functions of n inputs or eliminate some combinations? –What inputs go to what pieces of the function? n Any specialized logic? –Adder, etc. n What register features?

24. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Interconnect questions n How many wires in each channel? n Uniform distribution of wiring? n How should wires be segmented? n How rich is interconnect between channels? n How long is the average wire? n How much buffering do we add to wires?

25. FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR I/O block questions n How many pins? –Maximum number of pins determined by package type. n Are pins programmed individually or in groups? n Can all pins perform all functions? n How many logic families do we support?