1. 7-1 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon MOS Inverter — All essential features of MOS logic gates DC and transient characteristics. Load device out driver in

2. 7-2 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Load device R (Saturated) Enhancement Load Depletion Load V T <0 + + CMOS PMOS Pseudo-NMOS

3. 7-3 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon The basic inverter Pull-up out Pull-down IN V DD I DS Load line analysis V DD 1 2 3 4 V DS =V out I DS V out V in 1 2 3 4

4. 7-4 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Different Load Devices R IdId V DD Sat. Enh I d  (V DD -V T ) 2 Depi V out V dd Depl R V in V DS

5. 7-5 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon The basic Inverter  Ratioed IN out + + V out :Logic 0 value depends on Load resistance. V in =1  Static power consumption.

6. 7-6 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon  Ratioless out IN + V out Logic levels independent of resistance ratio’s No static power

7. 7-7 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Voltage Transfer characteristic-Depletion Load V out V in V out = V in 21 3 45 V in V out 1  2: driver off, load un-sat V in < V TD, V out  V dd V DS,driver  V dd, V DS,Load  0, (V GSL - V TL )>0 2  3: driver SAT, Load un-sat V TD < V in, vout  1/2 V dd (V GSD - V TD ) V DSL 3  4: driver SAT, Load SAT V in  1/2 V dd, V out :1/2 V dd  V OL V GSD - V TD  V DSD, (V GSL - V TL )< V DSL 4  5: driver un-sat, Load SAT V in  V dd, V out  V OL

8. 7-8 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Depletion Load V in =0 V in > V th SAT off V in V OL =? V out = V DD - V DS,Load  V DD V GS = 0 : V DS  5V : SAT(Load) V GS  5V : V DS  OV : Linear(Driver)

9. 7-9 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon (sat) (linear) Current in Load = current in driver 0

10. 7-10 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Depletion Load

11. 7-11 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 4:1 8:1 VxVx V dd V in V0V0 V out V in = V out V x  3.6V 5V 4:1 8:1 V inv

12. 7-12 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Ratioed Design (4:1, 8:1) L out IN + + V DD RLRL RDRD V out

13. 7-13 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon CMOS Inverter - No Ratioed design 1 2 3 4 6 5 V TN V mv V TP V in V out Driver SAT Load SAT       V dd IN out 1  2: Driver off, Load on 2  3: Driver SAT, Load Non-sat 3  4: Both in SAT 4  5: Driver Non-sat, Load SAT 5  6: Driver on, Load off

14. 7-14 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon I switch V TN V inv V DD - V TP IDID V out V in =0V in =V dd V in =0  V inN  V inP

15. 7-15 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon V inv : Solved by equating SAT current equations

16. 7-16 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon   N /  P =1 V out = V in Smaller  N /  P Larger  N /  P Trip Point V inv V DD V in V out

17. 7-17 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon CMOS Inverter VOVO V in A B D C E V tn V DD /2V tp V DD Region A. 0< V in < V tn, V o = V DD, n cut off, p-linear Region B. V tn < V in < V DD /2, n-saturation, p-linear

18. 7-18 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Region C. V in = V DD /2, both n and p saturation Normally, we will use the technology which has V tn =- V tp and design  n =  p so that the logic threshold is half of V DD.

19. 7-19 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Region D. V DD /2<V in <V DD -V tp, n-linear, p-saturation Region E. V in  V DD - V tp, p-cut off, n-linear V o =0

20. 7-20 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon  What is the relation between transfer curve and  or K R ratio? V in VoVo  n /  p or K R decrease increase  How does the temperature affect the transfer curve? V in VoVo T decrease increase V

21. 7-21 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Noise Margin for Single Inverter — The maximum allowable noise voltage on the input of a gate so that the out put will not be affected V in VoVo Unity gain slope=-1 V OH V OL V IL V IH V DD V IL 0 VORVOR V DD VOLVOL Logic”0” range Logic”1” range NM H =V OH -V IH NM L =V IL -V OL For TTL logic V IL = 0.8V, V OH =2.4V V IH =2.0V, V OL =0.4V, NM L =NM H =0.4V

22. 7-22 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon For NMOS depletion load In the case of V tn = V tp =0.2V DD NM L = NM H =0.425 V DD or 2.13V if V DD =5V

23. 7-23 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Noise margin and  ratio NM L (CMOS)  n /  p NM H (CMOS) NM Noise margin and V tn, V tp Noise margin will increase as V tn or |V tp | increase. However, the speed will be slow down.

24. 7-24 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Pseudo NMOS inverter Use PMOS as an equivalent depletion load device. PMOS V DD On all the time become ratio circuit again As (W/L) PMOS increase VoVo V in Advantage: save pull-up device. Disadvantage: When NMOS “on”, it dissipates DC power. V OL High, noise margin lower. If the switching point of inverter was kept at V DD /2, and assume V tn = |V tp |=1V,  n /  p must be greater or equal to 6, in other words (W/L) n / (W/L) p  3 (assume  n  2  p ) Where are the applications?

25. 7-25 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Rise and Fall time Determination outIN CLCL in CLCL out CMOS Charging (rise) time Discharging (fall) time CLCL V in =0 CLCL V in =5

26. 7-26 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Depletion Load out IN CLCL CLCL CLCL V in =5 Charging Discharging

27. 7-27 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Using I.V Characteristics Equations CLCL VGVG 5V  OV 1PF VGVG V out I DS V DS V GS =5V

28. 7-28 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Using 1.2  m CMOS process parameter  2.2nsec

29. 7-29 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Charging C load With NMOS Transistor (pass gate/transistor) V G =5V V D =5V C L =1PF VGVG V out 5V V out <5V I DS V GS

30. 7-30 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon  5.3nsec Trip point  low

31. 7-31 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Switching Characteristics of a CMOS inverter out IN t V in (t)V dd 0.5V dd t tftf V out (t) 0.9V dd 0.1V dd tdtd trtr t d : Delay time (50%  50%) t r : Rise time (10%  90%) t f : Fall time (90%  10%)

32. 7-32 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon CLCL V DD VOVO V in V DD V in V out VOVO t tftf trtr t t 0.9V DD 0.1V DD Fall time t f t f = t f1 + t f2 t f1 : V O drops from 0.9V DD to V DD - V tn (NMOS in saturation mode) t f2 : V O drops from V DD - V tn to 0.1V DD (NMOS in linear mode) t f1 can be obtained by solving the following differential equation.

33. 7-33 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon t f2 Can be obtained by solving the following differential equation

34. 7-34 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon

35. 7-35 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Propagation Delay First order approximation: Assume:V tn = |V tp | = V T, V INV =V DD /2, fanout=N, step input C L =N C g V in V out CgCg W p /L p W n /L n t PHL  Cap loading  power  FO.

36. 7-36 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Similarly Generalized Time Relay Model Non-ideal input (not a step ftn but has a slope) Output loading Transistor as a resistor Input slope Proportionality factor (linear model)