1. New digital readout of HFRAMDON neutron counters Proposal Version 2

2. Present system Neutron counter adaptor board (2chn) To National Instruments ADC/counting/IO boards Gamma counter adaptor board (2chn) Will go away Power supply board

3. Proposal for upgrade Neutron counter adaptor board (2chn) Power supply board Interface board (counters with FPGA mezzanine ethernet Eventual ADC board Option: interconnect board Removal of Gamma counter boards frees 4 double slots in the crate. This allows us to place the new interface board(s) directly to the crate. The backplane will be cut in 2 pieces: the first board (BP1) interconnects the neutron counters and power supply boad; The second backplane board BP2 is fully dedicated to new readout interface boards Digital signals from/to neutron adaptor boards will be routed to new backplane board BP2 connector 1 using single wires. Analog signals from neutron adaptor boards boards will be routed to new backplane board BP2 connector 1 using single wires. ADC board is connected to Interface board via backplane lines (carrying I2C signals) (optionally: by the flat cable ) Optional: I2C bus

4. New backplane boards 1 2 32 C B A 1 2 32 1 2 1 2 BP1 BP2 BP1 is a “shorened” version of existing backplane. BP2 is to be produced (by CERN/MSU) BP2 will be equipped by 4 “VME type” 96 contact connectors (for example ERNI 214836). The corresponding connectors for interface board is ERNI 533402 Voltage at backplane2: +5V and +12V. Digital signals from the neuron counters will be routed to BP2/4, the analog ones will go top BP2/3 4 3 2 1

5. Proposed BP2 connector pinout BP2/4 (interface board) ABC 1Gnd 2NC 3+5V 4+12V 5NC 6-14Int bus 15NC 16N1 GNDN1 OnN1 CNT 17N2 GNDN2 OnN2 CNT …………. 30N15 GNDN15 OnN15 CNT 31N16 GNDN16 OnN16 CNT 32GND BP2/3 (ADC board) ABC 1Gnd 2NC 3+5V 4+12V 5NC 6-14Int bus 15NC 16N1 GNDN1 voltageN1 current 17N2 GNDN2 voltageN2 current …………. 30N15 GNDN15voltageN15 current 31N16 GNDN16 voltageN16 current 32GND

6. Very basic layout of communication protocol The INTERFACE BOARD is read out by HOST_COMPUTER via ethernet (TCP/IP) The read out rate could vary in ranch [01Hz – 10Hz] The interface board recognizes the following commands from HOST computer: READ – latch the counters/ADCs and initiate readout cycle CONFIGURE – get internal parameters ACKNOWLEDGE – acknowledge the interlock (see interlock logic slide) During read out cycle the interface board transmits to the HOST COMPUTER a package, which contanin: Timestamp (32 bit word) Counting rate for detector (16 32bit words) Interlock status (1bit) Detector voltages and currents (32 Xbit words), depending on type of ADC CONFIGURE command transmits from HOST PC to interface board 16 bits with detector ON/OFF commands (0-OFF, 1-ON)

7. Requirements for new interface board INPUT SIGNALS (digital) Counting, from backplane. 16 TTL signals from the neutron adaptors. Expected counting rate – up to 1Mhz. Pulse duration is approx. 500ns. Counting depth: 32bit. All 16 channels + internal timestamp have to be readout (latched) at the same time. Interlock signal, front panel. Open or closed relay contacts. If contacts are open, all the digital output signals has to be set to LOW (detectors are OFF). OUTPUT SIGNALS (digital) Onn/Off, to Backplane. 16 channels (TTL 5V). High level means “detector ON”. Low level means “detector OFF”. INTERNAL SIGNALS 1KHz oscillator + 32bit counter to produce the internal timestamp. This counter should be readout (latched) together with INPUT COUNTING SIGNALS. Interlock status. See slide INTERLOCK LOGICS. OTHERS i2C communication with ADC board

8. Interlock logics The device is INTERLOCKED if External relay contacts are not closed OR “ACKNOWLEDGE” command is not received ACKNOWLEDGE command could be issued either by software either by a button at front panel. After power cycling, the device should be initialized in INTERLOCKED state. The device state (INTERLOCKED or not) should be readable via software and eventually indicated via LED at front panel If the device is INTERLOCKED, all the neutron detectors should be OFF. (digital outputs are LOW). It is recommended to implement this feature at the level of ouput buffer, which pulls up the TTL signals to 5V. In this case the INTELOCK or ACKNOWLEDGE events don’t screw up the configuration (which detectors should be ON)

9. ADC board Each of 16 neutron adapters produces 2 analog signals: “detector voltage” and “detector current”. Both signals are voltages in range 0 to 7 volts, output resistance not less then XXX KOhm ADC accuracy should be not worse then 0.1 V ADC board is mounted in a dedicated slot in the crate and gets the input signals from the adaptor via backplane. ADC board communicates with interface board via I2C (or whatever other) interface using front panel connectors ADC board is powered via backplane (option: via front panel connector)

10. Mecchanics All the boards are 3U standard (100mm x 160mm)