1. University of Toronto,Toronto, Ontario, Canada 1 Circuit Research Labs, Intel Corporation, Hillsboro, OR Variations-Aware Low-Power Design with Voltage Scaling Navid Azizi, Muhammad M. Khellah 1, Vivek De 1 and Farid N. Najm

2. Introduction Power consumption is increasingly becoming the bottleneck in design Power consumption is increasingly becoming the bottleneck in design Datapath circuits have a high power density Datapath circuits have a high power density –High activity and switching –Dynamic power consumption still a relatively large component for total power –Heats up the surrounding area Lowering the supply voltage can lead to lower power consumption Lowering the supply voltage can lead to lower power consumption –It however also leads to lower performance

3. Input Replicate the Design For circuit where latency is not important For circuit where latency is not important –Replicate the circuit m times to obtain equal throughput Standard Voltage Circuit Low Voltage Circuit Low Voltage Circuit Low Voltage Circuit Low Voltage Circuit InputOutput A. P. Chandrakasan and R. W. Brodersen. Low Power Digital CMOS Design. Kluwer Academic Publishers, 1995.

4. Effect of WID Process Variations on Leakage Power When using a circuit, you have to run it at slowest speed that we’re assured all blocks in parallel will work When using a circuit, you have to run it at slowest speed that we’re assured all blocks in parallel will work Fast blocks will be run at slower speeds Fast blocks will be run at slower speeds –Are usually the leakiest instances –Will be leaking power for long periods of time Fast & Leaky Fast & Leaky Slow & Not Leaky Slow & Not Leaky Output Input

5. Goals Taking into consideration the effect of within-die process and temperature variations Taking into consideration the effect of within-die process and temperature variations –To find out how many instances we need in parallel to equal the throughput of the Standard-Voltage System –At what Supply Voltage are the power benefits the greatest?

6. Effect of Variations on Power When not considering WID Variations, optimal voltage is 0.3V When not considering WID Variations, optimal voltage is 0.3V After going to silicon, however energy/operation would be After going to silicon, however energy/operation would be –8.2X higher than expected –Only 20% lower than at Standard Voltage System When considering WID variations When considering WID variations –Choose a different supply voltage (0.4V) –Reduce Energy/Operation by 7.6X

7. Effect of Correlation on Number of Blocks When not taking WID variations into account When not taking WID variations into account –Number of Blocks underestimated by large amount With WID process variations With WID process variations –Number of Blocks needed range from 41 to 100

8. Temperature Variations As temperature increases As temperature increases –Large increase in leakage –Loss of power benefits @30C @30C –Optimal Voltage: 0.4V –Power Reduction: 7.6X @110C @110C –Optimal Voltage has moved –Power Reduction @0.4V: 3.1X @0.4V: 3.1X

9. Temperature Dependent Deactivation With increased temperature With increased temperature –Have higher performance Turn off some of the blocks Turn off some of the blocks –Maintain throughput –Reduce power –Keep optimal voltage at the same place @30C @30C –Power Reduction: 7.6X @110C without Deactivation @110C without Deactivation –Power Reduction: 3.1X @110C with Deactivation @110C with Deactivation –Power Reduction: 5.3X

10. Conclusion Showed that if WID variations are not considered, then the traditional approach to designing a Low- Voltage Parallel System loses much of its advantages Showed that if WID variations are not considered, then the traditional approach to designing a Low- Voltage Parallel System loses much of its advantages Showed new methodology that takes into consideration WID variations Showed new methodology that takes into consideration WID variations –Optimal Supply Voltage is higher than when not considering WID variations –Lots of power savings still possible: 7.6X reduction Showed novel technique to reduce power consumption with variations in operating temperature Showed novel technique to reduce power consumption with variations in operating temperature