1. 05/12/2014 Gerrit Jan Focker, BE/BI/PM 1 PSB-Injection H - and H 0 Dump detectors and Stripping Foil current measurement

2. 15/06/2015 2 Introduction u Two functions: u Security / interlock, u Measurement of signal level. u Signal shape: u Pulse-width up to more than 100 μs, down to 50ns. u Up to 4mA electric current from a H 0 detector foil, u Up to 8mA electric current from a H - detector foil, u One would like to measure “small” currents at least from the H - detectors. u A Stripping Foil breakdown may result in 80mA of electrical current from the H - detector, the security amplifiers should not or only just saturate at such input levels. u Each detector will consist of 2 foils. u BIAS of up to +/-32V can be applied to the detectors, u This bias voltage will also be used for continuity checking. u No electronics in the tunnel, coax cables will be used. u No risk radiation damage, allowing wider range of electronic components. u This construction allows separate amplifiers for measurement and interlocks. u Stripping Foils u Have local grounding resistance (here represented by the 5Ω resistance), u Use the same cable-type and amplifier as the dump-detectors. u Bias up to +/-32V.

3. 15/06/2015 3 Housing u One VME card per Booster Ring, u The special card: u 10 BNC connectors, 5 inputs and 5 outputs for OASIS, u 6 LEMO connections: u Interlock output, u Test output of the analog error signal used for the interlock, u Two looped through connectors for trigger 1, u Two looped through connectors for trigger 2. u One card (already existing) for the interlock management.

4. 15/06/2015 4 Amplifier Type - Timing u Most difficult part remains to measure 50ns pulse! u Always a fast output for OASIS. u Analog integrator: u Integrates up to ~1μs (Booster turn), u Additional gain for very short pulses. u Time-domain measurements with a precision of ~1μs (Booster turn). u Averaging done in FESA class. u Timing: u Beam is injected every ~1μs (Booster turn). u During this time the beam duration (bucket) is 650ns, u Remaining time will be used for conversion and discharging the integrator. u Two trigger inputs are foreseen: u For synchronisation with Booster turns (~1μs), u For an initial trigger to know where to start measuring.

5. Interlock system u As all electronics will be placed in one chassis with one Power Supply only there is no use to double the electronics for the interlock system. u As one wants to measure small 50ns signals any additional electronics will perturb this measurement. u Each Ring will have its VME-card, these four VME-cards will each have an external connection to an already existing card that will OR the signals and interfaces to the Interlock System. The output can be reset by FESA. u The Reference (Trigger-level) can be set from FESA. u The integrator signal can be read by FESA as well as by oscilloscope via a LEMO connector on the Front Panel. 15/06/2015 5

6. 6 Cabling, Rack-space u Each electrode is equipped with double wiring and two connectors. u Only one connector will be used. u The bias should be adjusted to 1 Volt minimum (positive or negative) to allow to test the continuity of the wiring permanently. u The electronics shall be situated in one of the racks RA361 or RA362. u Proposed cables: CC50 (C-50-6-1). It may be necessary to use patch- panels and use short RG58 cables at the cable-ends. u (Spare cables?)

7. 15/06/2015 7 Conclusions and remarks. u Designing a VME card and then using fast and sensitive electronics of course takes some time. It is planned to at least have a working prototype by summer 2015.