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CMPUT 229 - Computer Organization and Architecture I1 CMPUT229 - Fall 2003 Topic3: Instructions, The Language of the Machine José Nelson Amaral
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CMPUT 229 - Computer Organization and Architecture I2 Reading Assignment zChapter 3 of Hennessy and Patterson: ySections 3.1 to 3.5.
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CMPUT 229 - Computer Organization and Architecture I3 Basics of the MIPS Architecture The MIPS architecture has 32 integer registers numbered from 0 to 31. The register 0 always contain the value 0. By software convention these 32 integer registers are divided into subgroup and most of them are referred by a letter and a number. For instance, compilers usually use registers named $s0, $s1, … to contain variables in a C program. Registers named $t0, $t1, … are typically used to store temporary values generated during the computation, but that have no correspondents in the variables in the C program.
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CMPUT 229 - Computer Organization and Architecture I4 Compiling a C Assignment Using Registers C assignment: f = (g + h) - (i + j) Assumption: f $s0 g $s1 h $s2 i $s3 j $s4 MIPS assembly: add $t0, $s1, $s2# $t0 g + h add $t1, $s3, $s4# $t1 i + j sub $s0, $t0, $t1# f $t0 - $t1
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CMPUT 229 - Computer Organization and Architecture I5 When Operands are in Memory C assignment: A[12] = h + A[8] Assumption: h $s2 base of array A $s3 MIPS assembly: lw $t0, 32($s3)# $t0 A[8] add $t0, $s2, $t0# $t0 h + A[8] sw $t0, 48($s3)# A[12] $t0
![CMPUT Computer Organization and Architecture I5 When Operands are in Memory C assignment: A[12] = h + A[8] Assumption: h $s2 base of array A $s3 MIPS assembly: lw $t0, 32($s3)# $t0 A[8] add $t0, $s2, $t0# $t0 h + A[8] sw $t0, 48($s3)# A[12] $t0](http://images.slideplayer.com./33/10138405/slides/slide_5.jpg "CMPUT Computer Organization and Architecture I5 When Operands are in Memory C assignment: A[12] = h + A[8] Assumption: h $s2 base of array A $s3 MIPS assembly: lw $t0, 32($s3)# $t0 A[8] add $t0, $s2, $t0# $t0 h + A[8] sw $t0, 48($s3)# A[12] $t0")
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CMPUT 229 - Computer Organization and Architecture I6 Memory Organization In MIPS an integer is represented by 4 bytes. A memory address references a single byte. Therefore the difference between the addresses of two consecutive integers in memory is 4. For instance, if the numbers +19 10 and -105 10 were stored consecutively in memory at address 0x10001000, the memory would contain: (remember that -105 10 =10010111 2 ) 0x10001000 0x10001001 0x10001002 0x10001003 0x10001004 0x10001005 0x10001006 0x10001007 0x00 0x13 0xFF 0x97 AddressValue In this example, the memory address of +19 10 is 0x10001000, and the memory address of -105 10 is 4 bytes ahead at 0x10001004
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CMPUT 229 - Computer Organization and Architecture I7 Endianess 0x10001000 0x10001001 0x10001002 0x10001003 0x10001004 0x10001005 0x10001006 0x10001007 0x00 0x13 0xFF 0x97 AddressValue In the previous example, there are two ways to store +19 10 at the address 0x10001000 and -105 10 at the address 0x10001004: 0x10001000 0x10001001 0x10001002 0x10001003 0x10001004 0x10001005 0x10001006 0x10001007 0x13 0x00 0x97 0xFF AddressValue What is the difference?
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CMPUT 229 - Computer Organization and Architecture I8 Little-End and Big-End +19 10 = 0000 0000 0000 0000 0000 0000 0001 0011 +19 10 = 0x0000 0013 Little end of +19 10 Big end of +19 10 (binary) (hexadecimal) -105 10 = 1111 1111 1111 1111 1111 1111 1001 0111 +19 10 = 0xFFFF FF97 Little end of +19 10 Big end of +19 10 (binary) (hexadecimal)
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CMPUT 229 - Computer Organization and Architecture I9 Endianess 0x10001000 0x10001001 0x10001002 0x10001003 0x10001004 0x10001005 0x10001006 0x10001007 0x00 0x13 0xFF 0x97 AddressValue The question is: which end of the integer do we store first in memory? 0x10001000 0x10001001 0x10001002 0x10001003 0x10001004 0x10001005 0x10001006 0x10001007 0x13 0x00 0x97 0xFF AddressValue Big end of +19 10 Little end of +19 10 Little Endian Byte OrderBig Endian Byte Order DECstations and Intel 80x86 are little-endians. Sun SPARC and Macintosh are big-endians.
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CMPUT 229 - Computer Organization and Architecture I10 Addressing Memory MIPS assembly: lw $t0, 32($s3)# $t0 A[8] add $t0, $s2, $t0# $t0 h + A[8] sw $t0, 48($s3)# A[12] $t0 Now we can understand the lw and sw instructions in the MIPS Assembly: lw stands for “load word”, and sw stands for “store word”. A word is the most used data unit in a processor. In the MIPS a word has 4 bytes, or 32 bits. lw loads a word from an specified memory location into a register in the processor. sw stores a word from a register in the processor into the specified memory location.
![CMPUT Computer Organization and Architecture I10 Addressing Memory MIPS assembly: lw $t0, 32($s3)# $t0 A[8] add $t0, $s2, $t0# $t0 h + A[8] sw $t0, 48($s3)# A[12] $t0 Now we can understand the lw and sw instructions in the MIPS Assembly: lw stands for load word , and sw stands for store word .](http://images.slideplayer.com./33/10138405/slides/slide_10.jpg "A word is the most used data unit in a processor. In the MIPS a word has 4 bytes, or 32 bits. lw loads a word from an specified memory location into a register in the processor. sw stores a word from a register in the processor into the specified memory location..")
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CMPUT 229 - Computer Organization and Architecture I11 Addressing Memory MIPS assembly: lw $t0, 32($s3)# $t0 A[8] add $t0, $s2, $t0# $t0 h + A[8] sw $t0, 48($s3)# A[12] $t0 Destination register for lw Source register for sw Source memory location for lw Destination memory location for sw
![CMPUT Computer Organization and Architecture I11 Addressing Memory MIPS assembly: lw $t0, 32($s3)# $t0 A[8] add $t0, $s2, $t0# $t0 h + A[8] sw $t0, 48($s3)# A[12] $t0 Destination register for lw Source register for sw Source memory location for lw Destination memory location for sw](http://images.slideplayer.com./33/10138405/slides/slide_11.jpg "CMPUT Computer Organization and Architecture I11 Addressing Memory MIPS assembly: lw $t0, 32($s3)# $t0 A[8] add $t0, $s2, $t0# $t0 h + A[8] sw $t0, 48($s3)# A[12] $t0 Destination register for lw Source register for sw Source memory location for lw Destination memory location for sw")
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CMPUT 229 - Computer Organization and Architecture I12 Displacement Addressing Mode MIPS assembly: lw $t0, 32($s3)# $t0 A[8] add $t0, $s2, $t0# $t0 h + A[8] sw $t0, 48($s3)# A[12] $t0 32($s3) tells the processor to read the value stored in register $s3, add 32 (8 words) to it, and use the result as the memory address for the load instruction
![CMPUT Computer Organization and Architecture I12 Displacement Addressing Mode MIPS assembly: lw $t0, 32($s3)# $t0 A[8] add $t0, $s2, $t0# $t0 h + A[8] sw $t0, 48($s3)# A[12] $t0 32($s3) tells the processor to read the value stored in register $s3, add 32 (8 words) to it, and use the result as the memory address for the load instruction](http://images.slideplayer.com./33/10138405/slides/slide_12.jpg "CMPUT Computer Organization and Architecture I12 Displacement Addressing Mode MIPS assembly: lw $t0, 32($s3)# $t0 A[8] add $t0, $s2, $t0# $t0 h + A[8] sw $t0, 48($s3)# A[12] $t0 32($s3) tells the processor to read the value stored in register $s3, add 32 (8 words) to it, and use the result as the memory address for the load instruction")
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CMPUT 229 - Computer Organization and Architecture I13 Example of lw execution MIPS assembly: lw $t0, 32($s3)# $t0 A[8] $t0 $t1 $t2 $s0 $s1 $s2 $s3 + 32 Address Bus
![CMPUT Computer Organization and Architecture I13 Example of lw execution MIPS assembly: lw $t0, 32($s3)# $t0 A[8] $t0 $t1 $t2 $s0 $s1 $s2 $s Address Bus](http://images.slideplayer.com./33/10138405/slides/slide_13.jpg "CMPUT Computer Organization and Architecture I13 Example of lw execution MIPS assembly: lw $t0, 32($s3)# $t0 A[8] $t0 $t1 $t2 $s0 $s1 $s2 $s Address Bus")
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CMPUT 229 - Computer Organization and Architecture I14 Example of lw execution MIPS assembly: lw $t0, 32($s3)# $t0 A[8] $t0 $t1 $t2 $s0 $s1 $s2 $s3 + 32 Memory Cells Memory Controller Address Bus
![CMPUT Computer Organization and Architecture I14 Example of lw execution MIPS assembly: lw $t0, 32($s3)# $t0 A[8] $t0 $t1 $t2 $s0 $s1 $s2 $s Memory Cells Memory Controller Address Bus](http://images.slideplayer.com./33/10138405/slides/slide_14.jpg "CMPUT Computer Organization and Architecture I14 Example of lw execution MIPS assembly: lw $t0, 32($s3)# $t0 A[8] $t0 $t1 $t2 $s0 $s1 $s2 $s Memory Cells Memory Controller Address Bus")
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CMPUT 229 - Computer Organization and Architecture I15 Example of lw execution MIPS assembly: lw $t0, 32($s3)# $t0 A[8] $t0 $t1 $t2 $s0 $s1 $s2 $s3 + 32 Memory Cells Memory Controller Address Bus Data Bus
![CMPUT Computer Organization and Architecture I15 Example of lw execution MIPS assembly: lw $t0, 32($s3)# $t0 A[8] $t0 $t1 $t2 $s0 $s1 $s2 $s Memory Cells Memory Controller Address Bus Data Bus](http://images.slideplayer.com./33/10138405/slides/slide_15.jpg "CMPUT Computer Organization and Architecture I15 Example of lw execution MIPS assembly: lw $t0, 32($s3)# $t0 A[8] $t0 $t1 $t2 $s0 $s1 $s2 $s Memory Cells Memory Controller Address Bus Data Bus")
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CMPUT 229 - Computer Organization and Architecture I16 Example of sw execution MIPS assembly: sw $t0, 48($s3)# A[12] $t0 $t0 $t1 $t2 $s0 $s1 $s2 $s3 + 48 Address Bus Data Bus
![CMPUT Computer Organization and Architecture I16 Example of sw execution MIPS assembly: sw $t0, 48($s3)# A[12] $t0 $t0 $t1 $t2 $s0 $s1 $s2 $s Address Bus Data Bus](http://images.slideplayer.com./33/10138405/slides/slide_16.jpg "CMPUT Computer Organization and Architecture I16 Example of sw execution MIPS assembly: sw $t0, 48($s3)# A[12] $t0 $t0 $t1 $t2 $s0 $s1 $s2 $s Address Bus Data Bus")
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CMPUT 229 - Computer Organization and Architecture I17 Example of sw execution MIPS assembly: sw $t0, 48($s3)# A[12] $t0 $t0 $t1 $t2 $s0 $s1 $s2 $s3 + 48 Memory Cells Memory Controller Address Bus Data Bus
![CMPUT Computer Organization and Architecture I17 Example of sw execution MIPS assembly: sw $t0, 48($s3)# A[12] $t0 $t0 $t1 $t2 $s0 $s1 $s2 $s Memory Cells Memory Controller Address Bus Data Bus](http://images.slideplayer.com./33/10138405/slides/slide_17.jpg "CMPUT Computer Organization and Architecture I17 Example of sw execution MIPS assembly: sw $t0, 48($s3)# A[12] $t0 $t0 $t1 $t2 $s0 $s1 $s2 $s Memory Cells Memory Controller Address Bus Data Bus")
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CMPUT 229 - Computer Organization and Architecture I18 Example of sw execution MIPS assembly: sw $t0, 48($s3)# A[12] $t0 $t0 $t1 $t2 $s0 $s1 $s2 $s3 + 48 Memory Cells Memory Controller Address Bus Data Bus
![CMPUT Computer Organization and Architecture I18 Example of sw execution MIPS assembly: sw $t0, 48($s3)# A[12] $t0 $t0 $t1 $t2 $s0 $s1 $s2 $s Memory Cells Memory Controller Address Bus Data Bus](http://images.slideplayer.com./33/10138405/slides/slide_18.jpg "CMPUT Computer Organization and Architecture I18 Example of sw execution MIPS assembly: sw $t0, 48($s3)# A[12] $t0 $t0 $t1 $t2 $s0 $s1 $s2 $s Memory Cells Memory Controller Address Bus Data Bus")
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CMPUT 229 - Computer Organization and Architecture I19 Representing Instructions: R-Type Instructions add $t0, $s1, $s2# (R8 = $t0, R17 = $s1, R18 = $s2) 00000010001100100100000000100000 31 265 010 615 1120 1625 21 017188032 oprsrtrdshamtfunct R-Type Instruction Format op: Opcode to specify the type of instruction; rs:first register source operand rt: second register source operand rd:register destination operand shamt: used for shift instructions (we will examine them later) funct: function code, specify the variant of the instruction to be executed
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CMPUT 229 - Computer Organization and Architecture I20 Representing Instructions: R-Type Instructions add $t0, $s1, $s2# (R8 = $t0, R17 = $s1, R18 = $s2) 00000010001100100100000000100000 31 265 010 615 1120 1625 21 017188032 oprsrtrdshamtfunct R-Type Instruction Format In memory we would see: 0x02324020 op: Opcode to specify the type of instruction; rs:first register source operand rt: second register source operand rd:register destination operand shamt: used for shift instructions (we will examine them later) funct: function code, specify the variant of the instruction to be executed
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CMPUT 229 - Computer Organization and Architecture I21 Representing Instructions: R-Type Instructions add $t0, $s1, $s2# (R8 = $t0, R17 = $s1, R18 = $s2) 00000010001100100100000000100000 31 265 010 615 1120 1625 21 017188032 oprsrtrdshamtfunct R-Type Instruction Format In memory we would see: 0x02324020 op: Opcode to specify the type of instruction; rs:first register source operand rt: second register source operand rd:register destination operand shamt: used for shift instructions (we will examine them later) funct: function code, specify the variant of the instruction to be executed
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CMPUT 229 - Computer Organization and Architecture I22 Representing Instructions: R-Type Instructions add $t0, $s1, $s2# (R8 = $t0, R17 = $s1, R18 = $s2) 00000010001100100100000000100000 31 265 010 615 1120 1625 21 017188032 oprsrtrdshamtfunct R-Type Instruction Format In memory we would see: 0x02324020 op: Opcode to specify the type of instruction; rs:first register source operand rt: second register source operand rd:register destination operand shamt: used for shift instructions (we will examine them later) funct: function code, specify the variant of the instruction to be executed
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CMPUT 229 - Computer Organization and Architecture I23 Representing Instructions: I format Instructions lw $t0, 32($s3)# (R8 = $t0, R19 = $s3) # $t0 Memory[$s3 + 32] 10001110011010000000 0000 0010 0000 31 2615 020 1625 21 3519832 OpCodersrtaddress I-Type Instruction Format In memory we would see: 0x86680020
![CMPUT Computer Organization and Architecture I23 Representing Instructions: I format Instructions lw $t0, 32($s3)# (R8 = $t0, R19 = $s3) # $t0 Memory[$s3 + 32] OpCodersrtaddress I-Type Instruction Format In memory we would see: 0x](http://images.slideplayer.com./33/10138405/slides/slide_23.jpg "CMPUT Computer Organization and Architecture I23 Representing Instructions: I format Instructions lw $t0, 32($s3)# (R8 = $t0, R19 = $s3) # $t0 Memory[$s3 + 32] OpCodersrtaddress I-Type Instruction Format In memory we would see: 0x")
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CMPUT 229 - Computer Organization and Architecture I24 Representing Instructions: I format Instructions lw $t0, 32($s3)# (R8 = $t0, R19 = $s3) # $t0 Memory[$s3 + 32] 10001110011010000000 0000 0010 0000 31 2615 020 1625 21 3519832 OpCodersrtaddress I-Type Instruction Format In memory we would see: 0x8E680020
![CMPUT Computer Organization and Architecture I24 Representing Instructions: I format Instructions lw $t0, 32($s3)# (R8 = $t0, R19 = $s3) # $t0 Memory[$s3 + 32] OpCodersrtaddress I-Type Instruction Format In memory we would see: 0x8E680020](http://images.slideplayer.com./33/10138405/slides/slide_24.jpg "CMPUT Computer Organization and Architecture I24 Representing Instructions: I format Instructions lw $t0, 32($s3)# (R8 = $t0, R19 = $s3) # $t0 Memory[$s3 + 32] OpCodersrtaddress I-Type Instruction Format In memory we would see: 0x8E680020")
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CMPUT 229 - Computer Organization and Architecture I25 Representing Instructions: Memory Instructions sw $t0, 1200($t1) # (R8 = $t0, R9 = $t1) # Memory[$t1 + 1200] $t0 10101110001010000000 0100 1011 1000 31 2615 020 1625 21 43981200 OpCodersrtaddress I-Type Instruction Format In memory we would see: 0xAE2404B8
![CMPUT Computer Organization and Architecture I25 Representing Instructions: Memory Instructions sw $t0, 1200($t1) # (R8 = $t0, R9 = $t1) # Memory[$t ] $t OpCodersrtaddress I-Type Instruction Format In memory we would see: 0xAE2404B8](http://images.slideplayer.com./33/10138405/slides/slide_25.jpg "CMPUT Computer Organization and Architecture I25 Representing Instructions: Memory Instructions sw $t0, 1200($t1) # (R8 = $t0, R9 = $t1) # Memory[$t ] $t OpCodersrtaddress I-Type Instruction Format In memory we would see: 0xAE2404B8")
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CMPUT 229 - Computer Organization and Architecture I26 Representing Instructions: Memory Instructions sw $t0, 1200($t1) # (R8 = $t0, R9 = $t1) # Memory[$t1 + 1200] $t0 10101110001010000000 0100 1011 1000 31 2615 020 1625 21 43981200 OpCodersrtaddress I-Type Instruction Format In memory we would see: 0xAE2404B8
![CMPUT Computer Organization and Architecture I26 Representing Instructions: Memory Instructions sw $t0, 1200($t1) # (R8 = $t0, R9 = $t1) # Memory[$t ] $t OpCodersrtaddress I-Type Instruction Format In memory we would see: 0xAE2404B8](http://images.slideplayer.com./33/10138405/slides/slide_26.jpg "CMPUT Computer Organization and Architecture I26 Representing Instructions: Memory Instructions sw $t0, 1200($t1) # (R8 = $t0, R9 = $t1) # Memory[$t ] $t OpCodersrtaddress I-Type Instruction Format In memory we would see: 0xAE2404B8")
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CMPUT 229 - Computer Organization and Architecture I27 Instructions for Making Decisions C code: if (i == j) f = g + h; else f = g - h;... Assumption: f $s0 g $s1 h $s2 i $s3 j $s4 MIPS assembly: bne$s3, $s4, Else# if i j goto Else add $s0, $s1, $s2# f g + h jExit# goto Exit Else:sub$s0, $s1, $s2# f g - h Exit:...
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CMPUT 229 - Computer Organization and Architecture I28 Representing Instructions: Branch Instructions bne $s3, $s4, 8 PC PC + 4 if($1 $2) PC PC + 8 00010110011101000000 0000 0000 0010 31 2615 020 1625 21 519202 OpCodersrtaddress I-Type Instruction Format MIPS assembly: 0x1000 0000bne$s3, $s4, Else# if i j goto Else 0x1000 0004add $s0, $s1, $s2# f g + h 0x1000 0008jExit# goto Exit 0x1000 000C Else:sub$s0, $s1, $s2# f g - h 0x1000 0010 Exit:... In memory we would see: 0x16740002 R19 = $s3, R20=$s4 Internally the processor multiplies this constant by 4 to obtain the distance of 8 bytes required.
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CMPUT 229 - Computer Organization and Architecture I29 Representing Instructions: Jump Instructions j Exit PC concat(PC[31-28],IR[25-0])<<2 00001000 0000 0000 0000 0000 0000 0100 31 2625 0 24 OpCodeaddress I-Type Instruction Format MIPS assembly: 0x1000 0000bne$s3, $s4, Else# if I j goto Else 0x1000 0004add $s0, $s1, $s2# f g + h 0x1000 0008jExit# goto Exit 0x1000 000B Else:sub$s0, $s1, $s2# f g - h 0x1000 0010 Exit:... In memory we would see: 0x08000002
![CMPUT Computer Organization and Architecture I29 Representing Instructions: Jump Instructions j Exit PC concat(PC[31-28],IR[25-0])<< OpCodeaddress I-Type Instruction Format MIPS assembly: 0x bne$s3, $s4, Else# if I j goto Else 0x add $s0, $s1, $s2# f g + h 0x jExit# goto Exit 0x B Else:sub$s0, $s1, $s2# f g - h 0x Exit:...](http://images.slideplayer.com./33/10138405/slides/slide_29.jpg "In memory we would see: 0x")
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CMPUT 229 - Computer Organization and Architecture I30 Representing Instructions: Jump Instructions j Exit PC concat(PC[31-28],IR[25-0])<<2 00001000 0000 0000 0000 0000 0000 0100 31 2625 0 24 OpCodeaddress MIPS assembly: 0x1000 0000bne$s3, $s4, Else# if I j goto Else 0x1000 0004add $s0, $s1, $s2# f g + h 0x1000 0008jExit# goto Exit 0x1000 000B Else:sub$s0, $s1, $s2# f g - h 0x1000 0010 Exit:... PC 0001 0000 0000 0000 0000 0000 0001 0000 PC 0x1000 0010
![CMPUT Computer Organization and Architecture I30 Representing Instructions: Jump Instructions j Exit PC concat(PC[31-28],IR[25-0])<< OpCodeaddress MIPS assembly: 0x bne$s3, $s4, Else# if I j goto Else 0x add $s0, $s1, $s2# f g + h 0x jExit# goto Exit 0x B Else:sub$s0, $s1, $s2# f g - h 0x Exit:...](http://images.slideplayer.com./33/10138405/slides/slide_30.jpg "PC PC 0x")
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CMPUT 229 - Computer Organization and Architecture I31 While Loops C code: while (save[i] == k) i = i + j;... Assumption: i $s3 j $s4 k $s5 base of save[ ] $s6 MIPS assembly: Loop:add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[i] k goto Exit add$s3, $s3, $s4# i i + j jLoop# goto Loop Exit: How can we improve this code?
![CMPUT Computer Organization and Architecture I31 While Loops C code: while (save[i] == k) i = i + j;...](http://images.slideplayer.com./33/10138405/slides/slide_31.jpg "Assumption: i $s3 j $s4 k $s5 base of save[ ] $s6 MIPS assembly: Loop:add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[i] k goto Exit add$s3, $s3, $s4# i i + j jLoop# goto Loop Exit: How can we improve this code .")
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CMPUT 229 - Computer Organization and Architecture I32 While Loops C code: while (save[i] == k) i = i + j;... MIPS assembly: Loop:add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit add$s3, $s3, $s4# i i + j jLoop# goto Loop Exit: load save[i]
![CMPUT Computer Organization and Architecture I32 While Loops C code: while (save[i] == k) i = i + j;...](http://images.slideplayer.com./33/10138405/slides/slide_32.jpg "MIPS assembly: Loop:add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit add$s3, $s3, $s4# i i + j jLoop# goto Loop Exit: load save[i].")
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CMPUT 229 - Computer Organization and Architecture I33 While Loops C code: while (save[i] == k) i = i + j;... MIPS assembly: Loop:add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit add$s3, $s3, $s4# i i + j jLoop# goto Loop Exit: load save[i] save[i] k? Exit yes
![CMPUT Computer Organization and Architecture I33 While Loops C code: while (save[i] == k) i = i + j;...](http://images.slideplayer.com./33/10138405/slides/slide_33.jpg "MIPS assembly: Loop:add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit add$s3, $s3, $s4# i i + j jLoop# goto Loop Exit: load save[i] save[i] k. Exit yes.")
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CMPUT 229 - Computer Organization and Architecture I34 While Loops C code: while (save[i] == k) i = i + j;... MIPS assembly: Loop:add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit add$s3, $s3, $s4# i i + j jLoop# goto Loop Exit: load save[i] i i + j no save[i] k? Exit yes
![CMPUT Computer Organization and Architecture I34 While Loops C code: while (save[i] == k) i = i + j;...](http://images.slideplayer.com./33/10138405/slides/slide_34.jpg "MIPS assembly: Loop:add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit add$s3, $s3, $s4# i i + j jLoop# goto Loop Exit: load save[i] i i + j no save[i] k. Exit yes.")
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CMPUT 229 - Computer Organization and Architecture I35 While Loops C code: while (save[i] == k) i = i + j;... MIPS assembly: Loop:add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit add$s3, $s3, $s4# i i + j jLoop# goto Loop Exit: load save[i] goto Loop i i + j no save[i] k? Exit yes
![CMPUT Computer Organization and Architecture I35 While Loops C code: while (save[i] == k) i = i + j;...](http://images.slideplayer.com./33/10138405/slides/slide_35.jpg "MIPS assembly: Loop:add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit add$s3, $s3, $s4# i i + j jLoop# goto Loop Exit: load save[i] goto Loop i i + j no save[i] k. Exit yes.")
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CMPUT 229 - Computer Organization and Architecture I36 While Loops C code: while (save[i] == k) i = i + j;... load save[i] i i + j goto Loop no save[i] k? Exit yes i i + j no load save[i] save[i] k? Exit yes load save[i] save[i] = k? yes Exit no Before Improvement After Improvement
![CMPUT Computer Organization and Architecture I36 While Loops C code: while (save[i] == k) i = i + j;...](http://images.slideplayer.com./33/10138405/slides/slide_36.jpg "load save[i] i i + j goto Loop no save[i] k. Exit yes i i + j no load save[i] save[i] k. Exit yes load save[i] save[i] = k. yes Exit no Before Improvement After Improvement.")
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CMPUT 229 - Computer Organization and Architecture I37 While Loops load save[i] MIPS assembly: add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit Loop:add$s3, $s3, $s4# i i + j add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] beq$t0, $s5, Loop# if save[I] k goto Exit Exit:
![CMPUT Computer Organization and Architecture I37 While Loops load save[i] MIPS assembly: add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit Loop:add$s3, $s3, $s4# i i + j add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] beq$t0, $s5, Loop# if save[I] k goto Exit Exit:](http://images.slideplayer.com./33/10138405/slides/slide_37.jpg "CMPUT Computer Organization and Architecture I37 While Loops load save[i] MIPS assembly: add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit Loop:add$s3, $s3, $s4# i i + j add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] beq$t0, $s5, Loop# if save[I] k goto Exit Exit:")
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CMPUT 229 - Computer Organization and Architecture I38 While Loops load save[i] save[i] k? Exit yes MIPS assembly: add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit Loop:add$s3, $s3, $s4# i i + j add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] beq$t0, $s5, Loop# if save[i] k goto Exit Exit:
![CMPUT Computer Organization and Architecture I38 While Loops load save[i] save[i] k.](http://images.slideplayer.com./33/10138405/slides/slide_38.jpg "Exit yes MIPS assembly: add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit Loop:add$s3, $s3, $s4# i i + j add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] beq$t0, $s5, Loop# if save[i] k goto Exit Exit:.")
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CMPUT 229 - Computer Organization and Architecture I39 While Loops i i + j no load save[i] save[i] k? Exit yes MIPS assembly: add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit Loop:add$s3, $s3, $s4# i i + j add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] beq$t0, $s5, Loop# if save[i] k goto Exit Exit:
![CMPUT Computer Organization and Architecture I39 While Loops i i + j no load save[i] save[i] k.](http://images.slideplayer.com./33/10138405/slides/slide_39.jpg "Exit yes MIPS assembly: add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit Loop:add$s3, $s3, $s4# i i + j add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] beq$t0, $s5, Loop# if save[i] k goto Exit Exit:.")
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CMPUT 229 - Computer Organization and Architecture I40 While Loops i i + j no load save[i] save[i] k? Exit yes load save[i] MIPS assembly: add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit Loop:add$s3, $s3, $s4# i i + j add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] beq$t0, $s5, Loop# if save[i] k goto Exit Exit:
![CMPUT Computer Organization and Architecture I40 While Loops i i + j no load save[i] save[i] k.](http://images.slideplayer.com./33/10138405/slides/slide_40.jpg "Exit yes load save[i] MIPS assembly: add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit Loop:add$s3, $s3, $s4# i i + j add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] beq$t0, $s5, Loop# if save[i] k goto Exit Exit:.")
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CMPUT 229 - Computer Organization and Architecture I41 While Loops i i + j no load save[i] save[i] k? Exit yes load save[i] save[i] = k? yes Exit no MIPS assembly: add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit Loop:add$s3, $s3, $s4# i i + j add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] beq$t0, $s5, Loop# if save[i] k goto Exit Exit:
![CMPUT Computer Organization and Architecture I41 While Loops i i + j no load save[i] save[i] k.](http://images.slideplayer.com./33/10138405/slides/slide_41.jpg "Exit yes load save[i] save[i] = k. yes Exit no MIPS assembly: add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit Loop:add$s3, $s3, $s4# i i + j add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] beq$t0, $s5, Loop# if save[i] k goto Exit Exit:.")
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CMPUT 229 - Computer Organization and Architecture I42 While Loops i i + j no load save[i] save[i] k? Exit yes load save[i] save[i] = k? yes Exit no MIPS assembly: add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit Loop:add$s3, $s3, $s4# i i + j add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] beq$t0, $s5, Loop# if save[i] k goto Exit Exit:
![CMPUT Computer Organization and Architecture I42 While Loops i i + j no load save[i] save[i] k.](http://images.slideplayer.com./33/10138405/slides/slide_42.jpg "Exit yes load save[i] save[i] = k. yes Exit no MIPS assembly: add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] bne$t0, $s5, Exit# if save[I] k goto Exit Loop:add$s3, $s3, $s4# i i + j add$t1, $s3, $s3# $t1 2 * i add $t1, $t1, $t1# $t1 4 * i add$t1, $t1, $s6# $t1 Addr(save[i]) lw$t0, 0($t1)# $t0 MEM[save[i]] beq$t0, $s5, Loop# if save[i] k goto Exit Exit:.")
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CMPUT 229 - Computer Organization and Architecture I43 Set on Less Than Instruction C code: if (a < b) goto Less... Assumption: a $s0 b $s1 MIPS assembly: slt $t0, $s0, $s1 # if ($s0 < $s1) $t0 1 else $t0 0 bne $t0, $zero, Less # if $t0 0 goto Less... Less:
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CMPUT 229 - Computer Organization and Architecture I44 Case/Switch Statement We will use a jump address table to encode the values of the cases and the addresses of the sequence of instructions that should be executed in each case. MIPS has a jump register (jr) instruction to support jump address tables: jr $t1 is an unconditional jump to the address in register $t1
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CMPUT 229 - Computer Organization and Architecture I45 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k 4, goto Exit add$t1, $s5, $s5# $t1 2*k add$t1, $t1, $t1# $t1 4*k add$t1, $t1, $t4# $t1 Addr[JumpTable[k]] lw$t0, 0($t1)# $t0 JumpTable[k] jr$t0# jump to address in $t0
![CMPUT Computer Organization and Architecture I45 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k 4, goto Exit add$t1, $s5, $s5# $t1 2*k add$t1, $t1, $t1# $t1 4*k add$t1, $t1, $t4# $t1 Addr[JumpTable[k]] lw$t0, 0($t1)# $t0 JumpTable[k] jr$t0# jump to address in $t0](http://images.slideplayer.com./33/10138405/slides/slide_45.jpg "CMPUT Computer Organization and Architecture I45 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k 4, goto Exit add$t1, $s5, $s5# $t1 2*k add$t1, $t1, $t1# $t1 4*k add$t1, $t1, $t4# $t1 Addr[JumpTable[k]] lw$t0, 0($t1)# $t0 JumpTable[k] jr$t0# jump to address in $t0")
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CMPUT 229 - Computer Organization and Architecture I46 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k 4, goto Exit add$t1, $s5, $s5# $t1 2*k add$t1, $t1, $t1# $t1 4*k add$t1, $t1, $t4# $t1 Addr[JumpTable[k]] lw$t0, 0($t1)# $t0 JumpTable[k] jr$t0# jump to address in $t0 Step 1: Test if 0 k < 4
![CMPUT Computer Organization and Architecture I46 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k 4, goto Exit add$t1, $s5, $s5# $t1 2*k add$t1, $t1, $t1# $t1 4*k add$t1, $t1, $t4# $t1 Addr[JumpTable[k]] lw$t0, 0($t1)# $t0 JumpTable[k] jr$t0# jump to address in $t0 Step 1: Test if 0 k < 4](http://images.slideplayer.com./33/10138405/slides/slide_46.jpg "CMPUT Computer Organization and Architecture I46 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k 4, goto Exit add$t1, $s5, $s5# $t1 2*k add$t1, $t1, $t1# $t1 4*k add$t1, $t1, $t4# $t1 Addr[JumpTable[k]] lw$t0, 0($t1)# $t0 JumpTable[k] jr$t0# jump to address in $t0 Step 1: Test if 0 k < 4")
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CMPUT 229 - Computer Organization and Architecture I47 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k 4, goto Exit add$t1, $s5, $s5# $t1 2*k add$t1, $t1, $t1# $t1 4*k add$t1, $t1, $t4# $t1 Addr[JumpTable[k]] lw$t0, 0($t1)# $t0 JumpTable[k] jr$t0# jump to address in $t0 Step 2: multiply k by 4 to index 32 bit addresses: $t1 4*k
![CMPUT Computer Organization and Architecture I47 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k 4, goto Exit add$t1, $s5, $s5# $t1 2*k add$t1, $t1, $t1# $t1 4*k add$t1, $t1, $t4# $t1 Addr[JumpTable[k]] lw$t0, 0($t1)# $t0 JumpTable[k] jr$t0# jump to address in $t0 Step 2: multiply k by 4 to index 32 bit addresses: $t1 4*k](http://images.slideplayer.com./33/10138405/slides/slide_47.jpg "CMPUT Computer Organization and Architecture I47 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k 4, goto Exit add$t1, $s5, $s5# $t1 2*k add$t1, $t1, $t1# $t1 4*k add$t1, $t1, $t4# $t1 Addr[JumpTable[k]] lw$t0, 0($t1)# $t0 JumpTable[k] jr$t0# jump to address in $t0 Step 2: multiply k by 4 to index 32 bit addresses: $t1 4*k")
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CMPUT 229 - Computer Organization and Architecture I48 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k 4, goto Exit add$t1, $s5, $s5# $t1 2*k add$t1, $t1, $t1# $t1 4*k add$t1, $t1, $t4# $t1 Addr[JumpTable[k]] lw$t0, 0($t1)# $t0 JumpTable[k] jr$t0# jump to address in $t0 Step 3: Load address of Jump Table into $t1
![CMPUT Computer Organization and Architecture I48 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k 4, goto Exit add$t1, $s5, $s5# $t1 2*k add$t1, $t1, $t1# $t1 4*k add$t1, $t1, $t4# $t1 Addr[JumpTable[k]] lw$t0, 0($t1)# $t0 JumpTable[k] jr$t0# jump to address in $t0 Step 3: Load address of Jump Table into $t1](http://images.slideplayer.com./33/10138405/slides/slide_48.jpg "CMPUT Computer Organization and Architecture I48 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k 4, goto Exit add$t1, $s5, $s5# $t1 2*k add$t1, $t1, $t1# $t1 4*k add$t1, $t1, $t4# $t1 Addr[JumpTable[k]] lw$t0, 0($t1)# $t0 JumpTable[k] jr$t0# jump to address in $t0 Step 3: Load address of Jump Table into $t1")
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CMPUT 229 - Computer Organization and Architecture I49 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k 4, goto Exit add$t1, $s5, $s5# $t1 2*k add$t1, $t1, $t1# $t1 4*k add$t1, $t1, $t4# $t1 Addr[JumpTable[k]] lw$t0, 0($t1)# $t0 JumpTable[k] jr$t0# jump to address in $t0 Step 4: Load address of code for case in $t0
![CMPUT Computer Organization and Architecture I49 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k 4, goto Exit add$t1, $s5, $s5# $t1 2*k add$t1, $t1, $t1# $t1 4*k add$t1, $t1, $t4# $t1 Addr[JumpTable[k]] lw$t0, 0($t1)# $t0 JumpTable[k] jr$t0# jump to address in $t0 Step 4: Load address of code for case in $t0](http://images.slideplayer.com./33/10138405/slides/slide_49.jpg "CMPUT Computer Organization and Architecture I49 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly: slt$t3, $s5, $zero# Test if k < 0 bne $t3, $zero, Exit# if k<0, goto Exit slt$t3, $s5, $t2# Test if k < 4 beq$t3, $zero, Exit# if k 4, goto Exit add$t1, $s5, $s5# $t1 2*k add$t1, $t1, $t1# $t1 4*k add$t1, $t1, $t4# $t1 Addr[JumpTable[k]] lw$t0, 0($t1)# $t0 JumpTable[k] jr$t0# jump to address in $t0 Step 4: Load address of code for case in $t0")
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CMPUT 229 - Computer Organization and Architecture I50 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly (cont.): L0:add$s0, $s3, $s4# f i + j jExit L1:add$s0, $s1, $s2# f g + h jExit L2:sub$s0, $s1, $s2# f g - h jExit L3:sub$s0, $s3, $s4# i i - j Exit:...
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CMPUT 229 - Computer Organization and Architecture I51 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly (cont.): L0:add$s0, $s3, $s4# f i + j jExit L1:add$s0, $s1, $s2# f g + h jExit L2:sub$s0, $s1, $s2# f g - h jExit L3:sub$s0, $s3, $s4# i i - j Exit:...
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CMPUT 229 - Computer Organization and Architecture I52 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly (cont.): L0:add$s0, $s3, $s4# f i + j jExit L1:add$s0, $s1, $s2# f g + h jExit L2:sub$s0, $s1, $s2# f g - h jExit L3:sub$s0, $s3, $s4# i i - j Exit:...
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CMPUT 229 - Computer Organization and Architecture I53 Case/Switch Statement C code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break; } Assumptions: i $s3f $s0 j $s4g $s1 k $s5h $s2 4 $t2 Initial address of Jump Table $t4 MIPS assembly (cont.): L0:add$s0, $s3, $s4# f i + j jExit L1:add$s0, $s1, $s2# f g + h jExit L2:sub$s0, $s1, $s2# f g - h jExit L3:sub$s0, $s3, $s4# i i - j Exit:...
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