1. Lecture 9. MIPS Processor Design – Single-Cycle Processor Design Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E Computer System Education & Research

2. Korea Univ Single-Cycle MIPS Processor Again, microarchitecture (CPU implementation) is divided into 2 interacting parts  Datapath  Control 2

3. Korea Univ Single-Cycle Processor Design Let’s start with a memory access instruction - lw  Example: lw $2, 80($0) 3 STEP 1: Instruction Fetch

4. Korea Univ Single-Cycle Processor Design STEP 2: Decoding  Read source operands from register file 4 Example: lw $2, 80($0)

5. Korea Univ Single-Cycle Processor Design STEP 2: Decoding  Sign-extend the immediate 5 Example: lw $2, 80($0) module signext(input [15:0] a, output [31:0] y); assign y = {{16{a[15]}}, a}; endmodule

6. Korea Univ Single-Cycle Processor Design 6 Example: lw $2, 80($0) STEP 3: Execution  Compute the memory address

7. Korea Univ Single-Cycle Processor Design 7 Example: lw $2, 80($0) STEP 4: Execution  Read data from memory and write it back to register file

8. Korea Univ Single-Cycle Processor Design We are done with lw CPU starts fetching the next instruction from PC+4 8 module adder(input [31:0] a, b, output [31:0] y); assign y = a + b; endmodule adder pcadd1(pc, 32'b100, pcplus4);

9. Korea Univ Single-Cycle Processor Design Let’s consider another memory access instruction - sw  sw instruction needs to write data to data memory 9 Example: sw $2, 84($0)

10. Korea Univ Single-Cycle Processor Design Let’s consider arithmetic and logical instructions - add, sub, and, or  Write ALUResult to register file  Note that R-type instructions write to rd field of instruction (instead of rt ) 10

11. Korea Univ Single-Cycle Processor Design Let’s consider a branch instruction - beq  Determine whether register values are equal  Calculate branch target address (BTA) from sign-extended immediate and PC+4 11 Example: beq $4,$0, around

12. Korea Univ Single-Cycle Datapath Example 12 We are done with the implementation of basic instructions Let’s see how or instruction works out in the implementation

13. Korea Univ Single-Cycle Processor - Control 13 As mentioned, CPU is designed with datapath and control Now, let’s delve into the control part design

14. Korea Univ Control Unit 14 Opcode and funct fields come from the fetched instruction

15. Korea Univ ALU Implementation and Control 15 F 2:0 Function 000A & B 001A | B 010A + B 011not used 100A & ~B 101A | ~B 110A - B 111SLT N = 32 in 32-bit processor slt : set less than Example: slt $t0, $t1, $t2 // $t0 = 1 if $t1 < $t2 adder

16. Korea Univ Control Unit: ALU Control 16 ALUOp 1:0 Meaning 00Add 01Subtract 10Look at Funct 11Not Used ALUOp 1:0 FunctALUControl 2:0 00X010 (Add) X1X110 (Subtract) 1X 100000 ( add ) 010 (Add) 1X 100010 ( sub ) 110 (Subtract) 1X 100100 ( and ) 000 (And) 1X 100101 ( or ) 001 (Or) 1X 101010 ( slt ) 111 (SLT) Implementation is completely dependent on hardware designers But, the designers should make sure the implementation is reasonable enough Memory access instructions (lw, sw) need to use ALU to calculate memory target address (addition) Branch instructions (beq, bne) need to use ALU for the equality check (subtraction)

17. Korea Univ Control Unit: Main Decoder 17 Instruction Op 5:0 RegWriteRegDstAluSrcBranchMemWriteMemtoRegALUOp 1:0 R-type 000000 lw 100011 sw 101011 beq 000100 ALUOp 1:0 Meaning 00Add 01Subtract 10 Look at Funct field 11Not Used 1100010 1 0 0 0 100100 X 1 0 1 X X 0 1 0 X 01 0

18. Korea Univ How about Other Instructions? 18 Example: addi $t0, $t1, -14 Hmmm.. Now, we are done with the control part design Let’s examine if the design is able to execute other instructions  addi

19. Korea Univ Control Unit: Main Decoder 19 InstructionOp 5:0 RegWriteRegDstAluSrcBranchMemWriteMemtoRegALUOp 1:0 R-type 00000011000010 lw 10001110100100 sw 1010110X101X00 beq 0001000X010X01 addi 001000 10 1 0 0 0 00

20. Korea Univ How about Other Instructions? 20 Ok. So far, so good… How about jump instructions?  j

21. Korea Univ How about Other Instructions? 21 We need to add some hardware to support the j instruction  A logic to compute the target address  Mux and control signal

22. Korea Univ Control Unit: Main Decoder 22 InstructionOp 5:0 RegWriteRegDstAluSrcBranchMemWriteMemtoRegALUOp 1:0 Jump R-type 000000110000100 lw 100011101001000 sw 1010110X101X000 beq 0001000X010X010 addi 001000101000000 j 0001000XXX0XXX1 There is one more output in the main decoder to support the jump instructions Jump

23. Korea Univ Verilog Code - Main Decoder and ALU Control 23 module maindec(input [5:0] op, output memtoreg, memwrite, output branch, alusrc, output regdst, regwrite, output jump, output [1:0] aluop); reg [8:0] controls; assign {regwrite, regdst, alusrc, branch, memwrite, memtoreg, jump, aluop} = controls; always @(*) case(op) 6'b000000: controls <= 9'b110000010; // R-type 6'b100011: controls <= 9'b101001000; // lw 6'b101011: controls <= 9'b001010000; // sw 6'b000100: controls <= 9'b000100001; // beq 6'b001000: controls <= 9'b101000000; // addi 6'b000010: controls <= 9'b000000100; // j default: controls <= 9'bxxxxxxxxx; // ??? endcase endmodule module aludec(input [5:0] funct, input [1:0] aluop, output reg [2:0] alucontrol); always @(*) case(aluop) 2'b00: alucontrol <= 3'b010; // add 2'b01: alucontrol <= 3'b110; // sub default: case(funct) // RTYPE 6'b100000: alucontrol <= 3'b010; // ADD 6'b100010: alucontrol <= 3'b110; // SUB 6'b100100: alucontrol <= 3'b000; // AND 6'b100101: alucontrol <= 3'b001; // OR 6'b101010: alucontrol <= 3'b111; // SLT default: alucontrol <= 3'bxxx; // ??? endcase endmodule

24. Korea Univ Verilog Code – ALU 24 module alu(input [31:0] a, b, input [2:0] alucont, output reg [31:0] result, output zero); wire [31:0] b2, sum, slt; assign b2 = alucont[2] ? ~b:b; assign sum = a + b2 + alucont[2]; assign slt = sum[31]; always@(*) case(alucont[1:0]) 2'b00: result <= a & b2; 2'b01: result <= a | b2; 2'b10: result <= sum; 2'b11: result <= slt; endcase assign zero = (result == 32'b0); endmodule F 2:0 Function 000A & B 001A | B 010A + B 011not used 100A & ~B 101A | ~B 110A - B 111SLT

25. Korea Univ Single-Cycle Processor Performance How fast is the single-cycle processor? Clock cycle time (frequency) is limited by the critical path  The critical path is the path that takes the longest time  What do you think the critical path is? The path that lw instruction goes through 25

26. Korea Univ Single-Cycle Processor Performance Single-cycle critical path: T c = t pcq_PC + t mem + max(t RFread, t sext ) + t mux + t ALU + t mem + t mux + t RFsetup In most implementations, limiting paths are: memory (instruction and data), ALU, register file. Thus, T c = t pcq_PC + 2t mem + t RFread + 2t mux + t ALU + t RFsetup 26 ElementsParameter Register clock-to-Qt pcq_PC Multiplexert mux ALUt ALU Memory readt mem Register file readt RFread Register file setupt RFsetup

27. Korea Univ Single-Cycle Processor Performance Example 27 T c = t pcq_PC + 2t mem + t RFread + 2t mux + t ALU + t RFsetup = [30 + 2(250) + 150 + 2(25) + 200 + 20] ps = 950 ps ElementsParameterDelay (ps) Register clock-to-Qt pcq_PC 30 Multiplexert mux 25 ALUt ALU 200 Memory readt mem 250 Register file readt RFread 150 Register file setupt RFsetup 20 Assuming that the CPU executes 100 billion instructions to run your program, what is the execution time of the program on a single-cycle MIPS processor? Execution Time = (#instructions)(cycles/instruction)(seconds/cycle) = (100 × 10 9 )(1)(950 × 10 -12 s) = 95 seconds f c = 1/T c f c = 1/950ps = 1.052GHz