1. Konstantin Stefanov 05/10/2006 1 Detecting elements for the CALICE MAPS design How does the collected charge depend on 1.Diode size? 2.Diode position with respect to the NWELL? 3.Diode bias voltage? Questions

2. Konstantin Stefanov 05/10/2006 2 substrate (p+) Diodes V D reflected charge Setup NWELL +3.3V DxDw 0X MIP track ●The NWELL is 3 μm wide ●Diode size and position are variable ●The location of the MIP track is also variable * The finite length of this structure does not allow full charge collection – some error is introduced 25  m50  m

3. Konstantin Stefanov 05/10/2006 3 Question 1 - Diode size ● The MIP hits at X from the NWELL centre ● Diode size Dw is variable, Dx = 12 μm

4. Konstantin Stefanov 05/10/2006 4 Question 2 - Diode position with respect to the NWELL ● The MIP hits the centre of the NWELL (X=0) ● Diode size Dw and their distance from the NWELL Dx are variable

5. Konstantin Stefanov 05/10/2006 5 Question 3 - Diode bias voltage ● The MIP hits at distance 8 μm from centre of the NWELL ● Diode size Dw and bias are variable, distance from the NWELL Dx is fixed to 12 μm

6. Konstantin Stefanov 05/10/2006 6 A movie speaks more than 1000 words ● The MIP hits at distance 8 μm from the NWELL centre ● Diode size Dw = 4 μm, 12 μm from the NWELL centre Depletion regions under the diodes are  3 μm deep. This is clearly visible as the electron density in the depleted regions is small (charge is transported very quickly there – seen as “liquid flow”) Click to start/stop

7. Konstantin Stefanov 05/10/2006 7 Conclusions ● Surprisingly, increasing the diode size does not proportionally improve the collection efficiency ● Should the effect be much stronger in 3D ( ~(Dw) 2 rather than ~Dw)? ● Very important to verify in 3D ● Placing the diodes next to the NWELL has some effect on reducing the charge loss ● Diode bias voltage is minor effect ● Signal density decreases rapidly with time and distance: diodes become less efficient ● Interesting to see how this will look in 3D

8. Konstantin Stefanov 05/10/2006 8 Suggestion #1 ● How to maximize the collected charge? ● Make sure there is a diode near the MIP impact ● Very big diode? Most likely will cause too much capacitance ● Suggestion #1: Use many diodes on uniform grid Diodes 50  m NWELL Diode 50  m NWELL

9. Konstantin Stefanov 05/10/2006 9 Suggestions #2 and #3 Diode connected by extended n+ diffusion: Adds (more?) capacitance, but also collects more charge Diode connected with metal track: Metal track adds capacitance Suggestion #2: Use diffusion to connect the diodes Suggestion #3: Use circular diodes Depletion to substrate  3 μm Sidewall capacitance significant due to high doping: Depletion width  0.5 μm, dopant height  1 μm (Circles have the smallest circumference for given area)