1. Lab 2 Basic Gates in a PLD Module M2.3 Section 4.2 Experiment 2 (p. 63)

2. Experiment 2

4. CUPL Header

5. CUPL Comments

6. CUPL Inputs and Outputs

7. CUPL Logic Equations

8. CUPL Chip Diagram in.DOC File

9. Fuse Plot for !X

10. Structure of the GAL 16V8 PLD

11. Fuse Plot for !Y

12. Structure of the GAL 16V8 PLD

13. Fuse Plot for X & Y

14. Structure of the GAL 16V8 PLD

15. Fuse Plot for !(X & Y)

16. GAL 16V8 Polarity Control OE X A B C X closed B = 0 C = A ­ open B = 1 C = !A Polarity Pin

17. Fuse Plot for X & Y

18. Fuse Plot for !(X & Y)

19. Fuse Plot for X # Y

20. Structure of the GAL 16V8 PLD

21. Fuse Plot for !(X # Y)

22. Fuse Plot for X $ Y

23. Structure of the GAL 16V8 PLD

24. Fuse Plot for !(X $ Y)

25. JEDEC File

26. JEDEC File Header

27. JEDEC File Fuse Map

28. Experiment 2 Basic Gates Modify the file, Exp2.pld, by using pins 6 and 7 for the two inputs X and Y respectively. Modify the simulation file, Exp2.si on the web to use your header. Compile the program using WinCupl and run the simulation. Print out the chip diagram from the.DOC file. Print out the fuse maps. Program the GAL 16V8 chip.

29. Experiment 2 Basic Gates Connect pins 6 (X) and 7 (Y) to Out1 and Out0. Connect pins 12-15 to In4-In1. Print the truth table. Label each output column with the appropriate gate. Connect pins 16-19 to In4-In1. Print the truth table. Label each output column with the appropriate gate. Explain the fuse maps.