Download presentation
Presentation is loading. Please wait.
1
FEM Power: 1. The TestBench version of the FEM requires 5.0 VDC @ 2.7A for proper operation. 2. The FEM can be powered from a 6U VME crate or from a lab power supply (using optional pigtail power leads).
2
Initial Conditions: 1. Text entered here will appear in the the top border of each sub menu 2. The FEM powers on in VME mode. Select USB mode to allow PC operation 3. Select the appropriate HIGH SPEED CHANNEL ENABLE(s) 4. Activate the RST (reset) button followed by the Auto Init button
3
Forced Data Read Setup: Use the register read/ write function to setup FEM registers Register 0x04 is used to mask/unmask the FastOR signals for chips 00 - 13 Register 0x14 is used to mask/unmask the FastOR signals for chips 20 - 33 Register 0x24 is used to mask/unmask the FastOR signals for chips 40 - 53 Register 0x60 sets the maximum trigger rate 0x60 ~ 20 Hz., 0x40 ~ 40 Hz. Register 0x82 set to 0x01 enables the internal FastOR trigger Register 0x83 set to 0x01 disables the EXT_IN trigger
4
Write data to file Trigger rate Total number of events Optional stop after a certain # of events
5
EXT_IN (external trigger input) Test outputs (3) Test output selection jumpers
6
EXT_IN (external trigger input) Test outputs (3) Test output signal selection jumpers EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, EXT_input};
7
Register 0x80 controls the FastOR trigger configuration: Reg 0x80 = 0x00 OR of all FastOR signals Reg 0x80 = 0x01 FastOR signals from chips 00 - 13 are ANDED with the FastOR signals from chips 20 - 33 Reg 0x80 = 0x02 FastOR signals from chips 00 - 13 are ANDED with the FastOR signals from chips 40 - 53 Reg 0x80 = 0x03 FastOR signals from chips 20 - 33 are ANDED with the FastOR signals from chips 40 - 53 Reg 0x80 = 0x04 FastOR signals from chips 00 - 13 are ANDED with the FastOR signals from chips 20 - 33 and ANDED with the FastOR signals from chips 40 - 53
8
// FAST OR Trigger Combinations determined by DREG 0x80 always @ (DREG[8'h80]) begin case (DREG[8'h80]) 8'h00: FOtrigger <= FOin[0] | FOin[1] | FOin[2] | FOin[3] | FOin[4] | FOin[5]; 8'h01: FOtrigger <= (FOin[0] | FOin[1]) & (FOin[2] | FOin[3]); 8'h02: FOtrigger <= (FOin[0] | FOin[1]) & (FOin[4] | FOin[5]); 8'h03: FOtrigger <= (FOin[2] | FOin[3]) & (FOin[4] | FOin[5]); 8'h04: FOtrigger <= (FOin[0] | FOin[1]) & (FOin[2] | FOin[3]) & (FOin[4] | FOin[5]); endcase end Register 0x80 selects FastOR combinations:
![// FAST OR Trigger Combinations determined by DREG 0x80 (DREG[8 h80]) begin case (DREG[8 h80]) 8 h00: FOtrigger <= FOin[0] | FOin[1] | FOin[2] | FOin[3] | FOin[4] | FOin[5]; 8 h01: FOtrigger <= (FOin[0] | FOin[1]) & (FOin[2] | FOin[3]); 8 h02: FOtrigger <= (FOin[0] | FOin[1]) & (FOin[4] | FOin[5]); 8 h03: FOtrigger <= (FOin[2] | FOin[3]) & (FOin[4] | FOin[5]); 8 h04: FOtrigger <= (FOin[0] | FOin[1]) & (FOin[2] | FOin[3]) & (FOin[4] | FOin[5]); endcase end Register 0x80 selects FastOR combinations:](http://images.slideplayer.com./33/10146581/slides/slide_8.jpg "// FAST OR Trigger Combinations determined by DREG 0x80 (DREG[8 h80]) begin case (DREG[8 h80]) 8 h00: FOtrigger <= FOin[0] | FOin[1] | FOin[2] | FOin[3] | FOin[4] | FOin[5]; 8 h01: FOtrigger <= (FOin[0] | FOin[1]) & (FOin[2] | FOin[3]); 8 h02: FOtrigger <= (FOin[0] | FOin[1]) & (FOin[4] | FOin[5]); 8 h03: FOtrigger <= (FOin[2] | FOin[3]) & (FOin[4] | FOin[5]); 8 h04: FOtrigger <= (FOin[0] | FOin[1]) & (FOin[2] | FOin[3]) & (FOin[4] | FOin[5]); endcase end Register 0x80 selects FastOR combinations:")
9
always @ (DREG[8'h90][3:0]) begin case (DREG[8'h90][3:0]) 4'h0: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, EXT_input}; 4'h1: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, extTRIGp}; 4'h2: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, FOTRIGp}; 4'h3: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, FOTRIG}; 4'h4: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, FOout}; 4'h5: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, clock10}; 4'h6: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, clock40}; 4'h7: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, gtmLock}; 4'h8: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, GTM_lock}; 4'h9: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, HIT}; default: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, HIT}; 4'ha: EXT_out <= {2'b0, clock10, gtmL2latch}; 4'hb: EXT_out <= {2'b0, clock10, gtmL2count}; endcase end Register 0x90 selects EXT_out (test outputs):
![(DREG[8 h90][3:0]) begin case (DREG[8 h90][3:0]) 4 h0: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, EXT_input}; 4 h1: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, extTRIGp}; 4 h2: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, FOTRIGp}; 4 h3: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, FOTRIG}; 4 h4: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, FOout}; 4 h5: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, clock10}; 4 h6: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, clock40}; 4 h7: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, gtmLock}; 4 h8: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, GTM_lock}; 4 h9: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, HIT}; default: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, HIT}; 4 ha: EXT_out <= {2 b0, clock10, gtmL2latch}; 4 hb: EXT_out <= {2 b0, clock10, gtmL2count}; endcase end Register 0x90 selects EXT_out (test outputs):](http://images.slideplayer.com./33/10146581/slides/slide_9.jpg "(DREG[8 h90][3:0]) begin case (DREG[8 h90][3:0]) 4 h0: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, EXT_input}; 4 h1: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, extTRIGp}; 4 h2: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, FOTRIGp}; 4 h3: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, FOTRIG}; 4 h4: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, FOout}; 4 h5: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, clock10}; 4 h6: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, clock40}; 4 h7: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, gtmLock}; 4 h8: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, GTM_lock}; 4 h9: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, HIT}; default: EXT_out <= {FOout, trigger, FOTRIGp, GTM_trigger, trigger, GTM_trigger, HIT}; 4 ha: EXT_out <= {2 b0, clock10, gtmL2latch}; 4 hb: EXT_out <= {2 b0, clock10, gtmL2count}; endcase end Register 0x90 selects EXT_out (test outputs):")
10
//----------------------------------------------------------------------------------------------------------- // 0x00 modAD[15:8] 0x10 modAD[15:8]0x20 modAD[15:8]0x30 Detector ID[15:8] // 0x01 modAD[7:0] 0x11 modAD[7:0]0x21 modAD[7:0]0x31 Detector ID[7:0] // 0x02 flgWD[15:8] 0x12 flgWD[15:8]0x22 flgWD[15:8]0x32 debug MUX control // 0x03 flgWD[7:0] 0x13 flgWD[7:0]0x23 flgWD[7:0]0x33 FO ring buffer offset Channel[1:0] // 0x04 FOmask_A 0x14 FOmask_B0x24 FOmask_C0x34 FO ring buffer offset Channel[3:2] // 0x05 tx_fastOR_A 0x15 tx_fastOR_B0x25 tx_fastOR_C0x35 FO ring buffer offset Channel[5:4] // 0x06 tdoData[0] 0x16 tdoData[2]0x26 tdoData[4]0x36 sizeMatters // 0x07 tdoData[1] 0x17 tdoData[3]0x27 tdoData[5]0x37 -- // 0x08 temp0[0][9:8] 0x18 temp0[2][9:8]0x28 temp0[4][9:8]0x38 latchSelect // 0x09 temp0[0][7:0] 0x19 temp0[2][7:0]0x29 temp0[4][7:0]0x39 -- // 0x0a temp0[1][9:8] 0x1a temp0[3][9:8]0x2a temp0[5][9:8]0x3a FIFOdata[15:8] // 0x0b temp0[1][7:0] 0x1b temp0[3][7:0]0x2b temp0[5][7:0]0x3b FIFOdata[7:0] // 0x0c --0x1c --0x2c --0x3c tx test data / disable txChannel(s) // 0x0d -- 0x1d --0c2d --0x3d TDOdata (ascii) // 0x0e -- 0x1e --0x2e --0x3e firmware version // 0x0f -- 0x1f --0x2f --0x3f global reset // //----------------------------------------------------------------------------------------------------------- FEM Registers:
![// // 0x00 modAD[15:8] 0x10 modAD[15:8]0x20 modAD[15:8]0x30 Detector ID[15:8] // 0x01 modAD[7:0] 0x11 modAD[7:0]0x21 modAD[7:0]0x31 Detector ID[7:0] // 0x02 flgWD[15:8] 0x12 flgWD[15:8]0x22 flgWD[15:8]0x32 debug MUX control // 0x03 flgWD[7:0] 0x13 flgWD[7:0]0x23 flgWD[7:0]0x33 FO ring buffer offset Channel[1:0] // 0x04 FOmask_A 0x14 FOmask_B0x24 FOmask_C0x34 FO ring buffer offset Channel[3:2] // 0x05 tx_fastOR_A 0x15 tx_fastOR_B0x25 tx_fastOR_C0x35 FO ring buffer offset Channel[5:4] // 0x06 tdoData[0] 0x16 tdoData[2]0x26 tdoData[4]0x36 sizeMatters // 0x07 tdoData[1] 0x17 tdoData[3]0x27 tdoData[5]0x37 -- // 0x08 temp0[0][9:8] 0x18 temp0[2][9:8]0x28 temp0[4][9:8]0x38 latchSelect // 0x09 temp0[0][7:0] 0x19 temp0[2][7:0]0x29 temp0[4][7:0]0x39 -- // 0x0a temp0[1][9:8] 0x1a temp0[3][9:8]0x2a temp0[5][9:8]0x3a FIFOdata[15:8] // 0x0b temp0[1][7:0] 0x1b temp0[3][7:0]0x2b temp0[5][7:0]0x3b FIFOdata[7:0] // 0x0c --0x1c --0x2c --0x3c tx test data / disable txChannel(s) // 0x0d -- 0x1d --0c2d --0x3d TDOdata (ascii) // 0x0e -- 0x1e --0x2e --0x3e firmware version // 0x0f -- 0x1f --0x2f --0x3f global reset // // FEM Registers:](http://images.slideplayer.com./33/10146581/slides/slide_10.jpg "// // 0x00 modAD[15:8] 0x10 modAD[15:8]0x20 modAD[15:8]0x30 Detector ID[15:8] // 0x01 modAD[7:0] 0x11 modAD[7:0]0x21 modAD[7:0]0x31 Detector ID[7:0] // 0x02 flgWD[15:8] 0x12 flgWD[15:8]0x22 flgWD[15:8]0x32 debug MUX control // 0x03 flgWD[7:0] 0x13 flgWD[7:0]0x23 flgWD[7:0]0x33 FO ring buffer offset Channel[1:0] // 0x04 FOmask_A 0x14 FOmask_B0x24 FOmask_C0x34 FO ring buffer offset Channel[3:2] // 0x05 tx_fastOR_A 0x15 tx_fastOR_B0x25 tx_fastOR_C0x35 FO ring buffer offset Channel[5:4] // 0x06 tdoData[0] 0x16 tdoData[2]0x26 tdoData[4]0x36 sizeMatters // 0x07 tdoData[1] 0x17 tdoData[3]0x27 tdoData[5]0x37 -- // 0x08 temp0[0][9:8] 0x18 temp0[2][9:8]0x28 temp0[4][9:8]0x38 latchSelect // 0x09 temp0[0][7:0] 0x19 temp0[2][7:0]0x29 temp0[4][7:0]0x39 -- // 0x0a temp0[1][9:8] 0x1a temp0[3][9:8]0x2a temp0[5][9:8]0x3a FIFOdata[15:8] // 0x0b temp0[1][7:0] 0x1b temp0[3][7:0]0x2b temp0[5][7:0]0x3b FIFOdata[7:0] // 0x0c --0x1c --0x2c --0x3c tx test data / disable txChannel(s) // 0x0d -- 0x1d --0c2d --0x3d TDOdata (ascii) // 0x0e -- 0x1e --0x2e --0x3e firmware version // 0x0f -- 0x1f --0x2f --0x3f global reset // // FEM Registers:")
11
//----------------------------------------------------------------------------------------------------------- // 0x40 channelEnable 0x50 TrigDly(LSBs)0x60 holdCount(LSBs)0x70 clock on/off // 0x41 -- 0x51 TrigDly(MSBs) 0x61 holdCount(MSBs)0x71 Test mode on/off // 0x42 latchEnable 0x52 -- 0x62 FOout -> FDR_TRIG (Enab)0x72 Test data on/off // 0x43 -- 0x53 -- 0x63 EXT_in-> FOout (Disab)0x73 Pulse mode on/off // 0x44 -- 0x54 -- 0x64 mask chips 0-70x74 GTM mode on/off // 0x45 -- 0x55 -- 0x65 mask chips 8-11 0x75 VME mode on/off // 0x46 -- 0x56 -- 0x66 mask chips 12-23 0x76 SyncReg // 0x47 -- 0x57 -- 0x67 TRIG holdOff (Disab)0x77 -- // 0x48 -- 0x58 -- 0x68 --0x78 -- // 0x49 -- 0x59 -- 0x69 --0x79 -- // 0x4a -- 0x5a -- 0x6a --0x7a -- // 0x4b -- 0x5b -- 0x6b --0x7b -- // 0x4c -- 0x5c -- 0x6c --0x7c -- // 0x4d -- 0x5d -- 0c6d --0x7d -- // 0x4e -- 0x5e -- 0x6e --0x7e -- // 0x4f -- 0x5f -- 0x6f --0x7f -- // //----------------------------------------------------------------------------------------------------------- FEM Registers (cont.):
12
//----------------------------------------------------------------------------------------------------------- // 0x80 FO MUX 0x90 EXT_out MUX0xa0 --0xb0 VMEchannel# // 0x81 -- 0x91 -- 0xa1 --0xb1 VMEcommand // 0x82 FOout Enable 0x92 -- 0xa2 --0xb2 -- // 0x83 -- 0x93 -- 0xa3 --0xb3 -- // 0x84 -- 0x94 -- 0xa4 --0xb4 -- // 0x85 -- 0x95 -- 0xa5 --0xb5 -- // 0x86 autoTrigger 0x96 -- 0xa6 --0xb6 -- // 0x87 -- 0x97 -- 0xa7 --0xb7 -- // 0x88 -- 0x98 -- 0xa8 --0xb8 -- // 0x89 -- 0x99 -- 0xa9 --0xb9 -- // 0x8a -- 0x9a -- 0xaa --0xba -- // 0x8b -- 0x9b -- 0xab --0xbb -- // 0x8c -- 0x9c -- 0xac --0xbc JTAGmemEna // 0x8d -- 0x9d -- 0xad --0xbd -- // 0x8e -- 0x9e -- 0xae --0xbe JTAGpointer(MSBs) // 0x8f -- 0x9f -- 0xaf --0xbf JTAGpointer(LSBs) // //----------------------------------------------------------------------------------------------------------- FEM Registers (cont.):
13
//----------------------------------------------------------------------------------------------------------- // 0xc0 AP_DAC[0][9:8] 0xd0 AP_DAC[8][9:8] 0xe0 AP_DAC[16][9:8]0xf0 status0 // 0xc1 AP_DAC[0][7:0] 0xd1 AP_DAC[8][7:0] 0xe1 AP_DAC[16][7:0]0xf1 status1 // 0xc2 AP_DAC[1][9:8] 0xd2 AP_DAC[9][9:8] 0xe2 --0xf2 status2 // 0xc3 AP_DAC[1][7:0] 0xd3 AP_DAC[9][7:0] 0xe3 --0xf3 status3 // 0xc4 AP_DAC[2][9:8] 0xd4 AP_DAC[10][9:8] 0xe4 --0xf4 busyStatus // 0xc5 AP_DAC[2][7:0] 0xd5 AP_DAC[10][7:0] 0xe5 --0xf5 fifoStatus // 0xc6 AP_DAC[3][9:8] 0xd6 AP_DAC[11][9:8] 0xe6 --0xf6 tdoStatus // 0xc7 AP_DAC[3][7:0] 0xd7 AP_DAC[11][7:0] 0xe7 --0xf7 TDOFIFOcount // 0xc8 AP_DAC[4][9:8] 0xd8 AP_DAC[12][9:8] 0xe8 --0xf8 // 0xc9 AP_DAC[4][7:0] 0xd9 AP_DAC[12][7:0] 0xe9 --0xf9 // 0xca AP_DAC[5][9:8] 0xda AP_DAC[13][9:8] 0xea --0xfa JTAGdata(MSBs) // 0xcb AP_DAC[5][7:0] 0xdb AP_DAC[13][7:0] 0xeb --0xfb JTAGdata(LSBs) // 0xcc AP_DAC[6][9:8] 0xdc AP_DAC[14][9:8] 0xec --0xfc JTAG_WordCtr(MSBs); // 0xcd AP_DAC[6][7:0] 0xdd AP_DAC[14][7:0] 0ced --0xfd JTAG_WordCtr(LSBs); // 0xce AP_DAC[7][9:8] 0xde AP_DAC[15][9:8] 0xee --0xfe Version # // 0xcf AP_DAC[7][7:0] 0xdf AP_DAC[15][7:0] 0xef --0xff Serial # // //----------------------------------------------------------------------------------------------------------- FEM Registers (cont.):
![// // 0xc0 AP_DAC[0][9:8] 0xd0 AP_DAC[8][9:8] 0xe0 AP_DAC[16][9:8]0xf0 status0 // 0xc1 AP_DAC[0][7:0] 0xd1 AP_DAC[8][7:0] 0xe1 AP_DAC[16][7:0]0xf1 status1 // 0xc2 AP_DAC[1][9:8] 0xd2 AP_DAC[9][9:8] 0xe2 --0xf2 status2 // 0xc3 AP_DAC[1][7:0] 0xd3 AP_DAC[9][7:0] 0xe3 --0xf3 status3 // 0xc4 AP_DAC[2][9:8] 0xd4 AP_DAC[10][9:8] 0xe4 --0xf4 busyStatus // 0xc5 AP_DAC[2][7:0] 0xd5 AP_DAC[10][7:0] 0xe5 --0xf5 fifoStatus // 0xc6 AP_DAC[3][9:8] 0xd6 AP_DAC[11][9:8] 0xe6 --0xf6 tdoStatus // 0xc7 AP_DAC[3][7:0] 0xd7 AP_DAC[11][7:0] 0xe7 --0xf7 TDOFIFOcount // 0xc8 AP_DAC[4][9:8] 0xd8 AP_DAC[12][9:8] 0xe8 --0xf8 // 0xc9 AP_DAC[4][7:0] 0xd9 AP_DAC[12][7:0] 0xe9 --0xf9 // 0xca AP_DAC[5][9:8] 0xda AP_DAC[13][9:8] 0xea --0xfa JTAGdata(MSBs) // 0xcb AP_DAC[5][7:0] 0xdb AP_DAC[13][7:0] 0xeb --0xfb JTAGdata(LSBs) // 0xcc AP_DAC[6][9:8] 0xdc AP_DAC[14][9:8] 0xec --0xfc JTAG_WordCtr(MSBs); // 0xcd AP_DAC[6][7:0] 0xdd AP_DAC[14][7:0] 0ced --0xfd JTAG_WordCtr(LSBs); // 0xce AP_DAC[7][9:8] 0xde AP_DAC[15][9:8] 0xee --0xfe Version # // 0xcf AP_DAC[7][7:0] 0xdf AP_DAC[15][7:0] 0xef --0xff Serial # // // FEM Registers (cont.):](http://images.slideplayer.com./33/10146581/slides/slide_13.jpg "// // 0xc0 AP_DAC[0][9:8] 0xd0 AP_DAC[8][9:8] 0xe0 AP_DAC[16][9:8]0xf0 status0 // 0xc1 AP_DAC[0][7:0] 0xd1 AP_DAC[8][7:0] 0xe1 AP_DAC[16][7:0]0xf1 status1 // 0xc2 AP_DAC[1][9:8] 0xd2 AP_DAC[9][9:8] 0xe2 --0xf2 status2 // 0xc3 AP_DAC[1][7:0] 0xd3 AP_DAC[9][7:0] 0xe3 --0xf3 status3 // 0xc4 AP_DAC[2][9:8] 0xd4 AP_DAC[10][9:8] 0xe4 --0xf4 busyStatus // 0xc5 AP_DAC[2][7:0] 0xd5 AP_DAC[10][7:0] 0xe5 --0xf5 fifoStatus // 0xc6 AP_DAC[3][9:8] 0xd6 AP_DAC[11][9:8] 0xe6 --0xf6 tdoStatus // 0xc7 AP_DAC[3][7:0] 0xd7 AP_DAC[11][7:0] 0xe7 --0xf7 TDOFIFOcount // 0xc8 AP_DAC[4][9:8] 0xd8 AP_DAC[12][9:8] 0xe8 --0xf8 // 0xc9 AP_DAC[4][7:0] 0xd9 AP_DAC[12][7:0] 0xe9 --0xf9 // 0xca AP_DAC[5][9:8] 0xda AP_DAC[13][9:8] 0xea --0xfa JTAGdata(MSBs) // 0xcb AP_DAC[5][7:0] 0xdb AP_DAC[13][7:0] 0xeb --0xfb JTAGdata(LSBs) // 0xcc AP_DAC[6][9:8] 0xdc AP_DAC[14][9:8] 0xec --0xfc JTAG_WordCtr(MSBs); // 0xcd AP_DAC[6][7:0] 0xdd AP_DAC[14][7:0] 0ced --0xfd JTAG_WordCtr(LSBs); // 0xce AP_DAC[7][9:8] 0xde AP_DAC[15][9:8] 0xee --0xfe Version # // 0xcf AP_DAC[7][7:0] 0xdf AP_DAC[15][7:0] 0xef --0xff Serial # // // FEM Registers (cont.):")
Similar presentations
