1. Plans for the 2015 Run Michal Koval, Peter Lichard and Vito Palladino TDAQ Working Group 25/3/2015

2. Hardware Gas leak to repair in Station 4 HV discharge in Station 4 to be understood SBC ◦ Move to local accounts (AFS is not stable enough) COVER ◦ Make safer the masking of the channels ◦ Check the multi-hit and FIFO full flags SRB ◦ Boards removed from the experiment (March the 5 th ) ◦ Fix the NIM outputs:  Boards machinery (1 VIA removed/board)  Patch to be applied on all boards starting from 8 of April ◦ Heat sinks installation ◦ Trigger matching  Testing software  Test bench 2 Done In Progress NOT Started

3. Hardware II One DATA cable to be changed in Station 1 Installation of the shielding for the cable trays (Reminder: the data cables are RJ45 but the signals are LVDS) Gain monitor module Full development setup in 154 (16 covers,1 or 2 SRB(s) and a complete MPOD system) 16ch ISEG HV module repairing Temperature sensors to be installed on the manifolds 3 Done In Progress NOT Started

4. Run Control Init procedure: ◦ Recognize PLLs problems + automatic actions ( => restart ALL the PLLs ) ◦ Recognize links problems + automatic actions ◦ Add masking of not connected straws ◦ Add reset of internal links SOB/EOB ◦ Automatic checks + actions:  Masks  Connection to COVERs  Thresholds  PLLs  Noise spikes (induced) Automatic reload of COVER parameters in case of reset Readout of the HW configuration 4 Done In Progress NOT Started

5. VME Monitoring (0-bias Data Sample) Produce the FW to access the data via VME Use 2014 raw data to produce test samples Generate histograms and optimization of the histograms update 5 Done In Progress NOT Started

6. Raw Data Analysis Toy Montecarlo to estimate the data throughput in case of trigger matching, with various trigger rates. Exercise the trigger algorithm(s) Generate a root tree from the raw data (Straw only) Data merging Searching for problems in COVERs connectivity ◦ Multi-hit and FULL full flags ◦ Noise spikes 6 Done In Progress NOT Started

7. CIRCULAR BUFFER ~ 1 ms INPUT FIFO 25ns SLICE DEPTH MEMORY (# of hits per time slice) 8,16 or 32 hits 8bit straw addr 5b fine time 1b edge 2b monitoring 1-2b coarse time OUTPUT FIFO FROM FRONTEND TO ETHERNET COARSE TIME COUNTER TTC SOB TIME REORDER 10us TRIGGER QUEUE TTC L0 CLEARING

8. 25ns Structure 8

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11. Conclusions and Plans L0 HW trigger matching is ongoing FW structure has been defined, all the parameters chosen Test software is ready to be tested Test bench in 154 is almost ready Looking forward to be part of the general TDAQ (mid of April, first planned for the end of this month) 11