1. Memory system 2015.01.30 Kang Min Ju

2. 01 Memory map NVIC : Nested Vector Interrupt Controller MPU : Memory Protection Unit * This arrangement allows: 1.support different types of memories and devices. 2.optimized arrangement for higher performance.

3. 02 Connecting the processor to memory and peripherals In order to provide better performance, the CODE memory region has separated the bus interfaces from the system bus. 1)data accesses and instruction fetches can be carried out in parallel. 2) The separate bus arrangement improve the interrupt responsiveness. The Cortex-M processors provide generic bus interfaces based on AMBA (Advanced Microcontroller Bus Architecture). In the Cortex-M3 and Cortex-M4 processors, 1. the AHB (AMBA High-performance Bus) Lite protocol is used for the main bus interfaces 2. the APB protocol is used for the Private Peripheral Bus (PPB), and is mainly used for debug components.

4. 02 Connecting the processor to memory and peripherals In a simple microcontroller design, 1.the program memory is connected to the I-CODE and D-CODE bus. 2. the SRAM and peripherals are connected to the system bus. In a number of Cortex-M3 and Cortex-M4 microcontroller products, You find multiple peripheral bus segments multiple bus masters Multiple peripheral bus segments allow 1) each bus operates different speeds for best power optimization 2) higher system bandwidth

5. 02 Connecting the processor to memory and peripherals Multiple bus masters on internal bus system such as DMA, Ethernet, USB 1) two bus masters are trying to access the same bus slave segment at the same time. 2) there are multiple SRAM blocks in separate AHB slave bus segments. Next

6. 03 Memory endianness The Cortex-M3 and Cortex-M4 processors determine the endianness of the memory system at a system reset. Most of the existing Cortex-M microcontrollers are little endian. (refer to the datasheet or reference materials) With a little endian memory system, the first byte of word-size data is stored in the least significant byte of the 32-bit memory location. With a big endian memory system, the first byte of word-size data is stored in the most significant byte of the 32-bit address memory location

7. 03 Memory endianness In the Cortex-M processors : Instruction fetches are always in little endian. Access to 0xE0000000 to 0xE00FFFFF are always little endian. (including System Control Space (SCS), debug components, and Private Peripheral Bus (PPB)) Ex) If software application needs to process big endian data and the microcontroller is little endian, you can convert the data between little endian and big endian using instructions such as REV, REVSH, and REV16. Next

8. 04 Data alignment and unaligned data access support : the address value is a multiple of the size (in bytes). Ex) With a 4-byte bus, aligned transfers must have a starting address that is a multiple of 4 (i.e., 0, 4, 8, etc.), and their total size must be a multiple of 4. Traditionally, most classic ARM processors (such as the ARM7/9/10) allow only aligned transfers. The Cortex-M3 and Cortex-M4 processors support unaligned data transfers in normal memory accesses (e.g., LDR, LDRH, STR, STRH instructions). 1) Be converted into multiple aligned transfers by the processor’s bus interface unit. 2) when it takes place, it is broken into several separate aligned transfers and it takes more clock cycles for a single data access -> Not Good! As a result, To get the best performance, data are aligned properly. Next

9. Bit-band operation allows a single load/store operation to access (read/write) to a single data bit. In the Cortex-M3 and Cortex-M4 processors, this is supported in two pre-defined memory regions called bit-band regions. 1) the first 1MB of the SRAM region, 2) the first 1MB of the peripheral region. To access these two memory regions, 1.Access like normal memory 2.Access via a separate memory region called the bit-band alias. The Cortex-M3 and Cortex-M4 processors do not have special instructions for bit operation. But special memory regions are defined, so that data accesses to these regions are automatically converted into bit-band operations. 05 Bit-band operations

10. There is no native support of bit-band operations in C/C++ languages. To use the bit-band feature in C, the simplest solution is 1)to separately declare the address and the bit-band alias of a memory location. 2) to develop C macros to make accessing the bit-band alias easier. ex) 05 Bit-band operations

11. 06 Memory access attributes In the Cortex-M3 and Cortex-M4 processors, The memory attributes include the following: Bufferable : While the processor continues on to next instruction execution, write to memory can be carried out by a write buffer. Cacheable : Data obtained from memory read can be copied to a memory cache so that next time it is accessed Executable : The processor can fetch and execute program code from this memory region. Sharable : Data in this memory region could be shared by multiple bus masters. The processor bus interfaces output the memory access attribute information.

12. 06 Memory access attributes In most existing Cortex-M3 and Cortex-M4 microcontrollers, 1) only the Executable and Bufferable attributes affect the operation of the applications. 2) The Cacheable and Sharable attributes are usually used by a cache controller. 3) The Cacheable and Bufferable attributes -> 1. The Sharable memory attribute is needed in systems with multiple processors and multiple cache units with cache coherency control.

13. 06 Memory access attributes 2. The Bufferable attribute is used inside the processor. There is a single entry write buffer on the bus interface. => Through the actual transfer needs several clock cycles to be completed on the bus interface, A data write to a bufferable memory region can be carried out in a single clock cycle and continue to the next instruction execution. 3. Default Memory Attributes The “XN” in the table is eXecute Never, : program execution in this region is prohibited. Next

14. 07 Exclusive accesses The Cortex-M3 and Cortex-M4 processors has no SWP instruction (swap). It was used for semaphore operations in traditional ARM processors. This is now being replaced by exclusive access operations. To allow exclusive access to work properly in a multiple processor environment, 1.An additional hardware unit is required called the “exclusive access monitor”. This monitor checks the transfers toward shared address locations and replies to the processor if an exclusive access is successful. 2. The processor bus interface also provides additional control signals to this monitor to indicate if the transfer is an exclusive access.

15. 07 Exclusive accesses In the Cortex-M3 and Cortex-M4 processors, Exclusive access instructions include Load : LDREX (word), LDREXB (byte), LDREXH (half word), Store : STREX (word), STREXB (byte), and STREXH (half word). A simple example of the syntax is as follows: LDREX, [Rn, #offset] STREX,,[Rn, #offset] where Rd is the return status of the exclusive write (0 = success and 1 = failure). When exclusive accesses are used, the internal write buffers will be bypassed in the processor’s bus interface, even when the MPU defines the region as bufferable. Next

16. 08 Memory barriers In most applications running in Cortex-M3 and Cortex-M4 microcontrollers, omission of memory barrier instructions does not cause any issues because: The Cortex-M3 and Cortex-M4 processors do not re-order any memory transfers or instruction execution The simple nature of the AHB Lite and APB protocol does not allow a transfer to start before the previous one finishes. Next

17. 09 Memory system in a microcontroller In many microcontroller devices, the designs integrate additional memory system features such as: Boot loader Memory remapping Memory alias Very often the separate program memory contains a boot loader, which is a program that executes before your own application starts. The next time the system starts, it might not need to execute the boot loader again and can run the application in the flash directly. In sequence, in order that the memory map needs to be changed, the address decoder needs to be programmable. A hardware register can be used. (e.g., a peripheral register in a system control unit)

18. 09 Memory system in a microcontroller The operation to switch the memory map is called “Memory Remap.” This operation is done by the boot loader. (Figure) But at the same time, you cannot switch the memory map and branch to the new location of the boot loader. So a method called alias is used. With memory address alias, the boot loader ROM is accessible from two different memory regions. End

19. Fault Exceptions and Fault Handling

20. All these issues could lead to failure in the programs running on the processors. In many simple microcontrollers, you can find features like a watchdog timer and Brown-Out Detector (BOD). The watchdog can be programmed to trigger if the counter is not cleared within a certain time, and can be used to generate a reset or Non-Maskable Interrupt (NMI). The BOD can be used to generate a reset if the supply voltage drops to a certain critical level. In many ARM microcontrollers for some safety critical applications, When a failure occurs and the processor stops responding, it might take a bit of time for the watchdog to kick in. 00 Overview

21. In order to allow problems to be detected as early as possible, the Cortex-M processors have a fault exception mechanism included. By default, all the faults trigger the HardFault exception (exception type number 3). The Cortex-M3 and Cortex-M4 processors have three additional configurable fault exception handlers: MemManage (Memory Management) Fault (exception type 4) Bus Fault (exception type 5) Usage Fault (exception type 6) These exceptions are triggered 1) if they are enabled. 2) if their priority is higher than the current exception priority level. 00 Overview Next

22. 01 [1] Causes of faults [2] Enabling fault handlers : By default the configurable fault exceptions are disabled. You can enable these exceptions by writing to System Handler Control and State Register (SCB->SHCSR). [3] Fault status registers and fault address registers : The Cortex-M3 and Cortex-M4 processors have a number of registers that are used for fault analysis. These registers can only be accessed in privileged state.

23. MemManage faults can 1) be caused by violation of access rules defined by the MPU configurations. 2) be triggered when trying to execute program code in eXecute Never (XN) regions such as the PERIPHERAL region, DEVICE region, or SYSTEM region. Enable the MemManage Fault exception handler SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; //Set bit 16 The default name for MemManage Fault exception handler (as defined in CMSIS-Core) void MemManage_Handler(void); Set up the priority of the MemManage Fault NVIC_SetPriority(MemoryManagement_IRQn, priority); Each fault indication status bit (not including MMARVALID) 1)be set when the fault occurs, 2)stay high until a value of 1 is written to the register. 01 1.Memory management (MemManage) faults

24. 01 2. Bus faults The bus faults can 1) be triggered by error responses received from the processor bus interface during a memory access. ex) Instruction fetch (read), Data read or data write 2) occur during stacking and unstacking of the exception handling sequence. Enable the Bus Fault exception handler SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk; //Set bit 17 The default name for the Bus Fault exception handler (as defined in CMSIS-Core) void BusFault_Handler(void); Set up the priority of the Bus Fault NVIC_SetPriority(BusFault_IRQn, priority); Each fault indication status bit (not including BFARVALID) 1)be set when the fault occurs, 2)stay high until a value of 1 is written to the register.

25. 01 3. Usage faults The Usage Fault exception can be caused by a wide range of factors: Execution of an undefined instruction Execution of Co-processor instructions Trying to switch to ARM state etc.. Enable the Usage Fault exception handler SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk; //Set bit 18 The default name for the Usage Fault exception handler (as defined in CMSIS-Core) void UsageFault_Handler(void); Set up the priority of the Usage Fault NVIC_SetPriority(UsageFault_IRQn, priority); Each fault indication status bit 1)be set when the fault occurs, 2)stay high until a value of 1 is written to the register.

26. 01 4. HardFaults The HardFault exception can be triggered by escalation of configurable fault exceptions. There is no need to enable the HardFault handler. This is always enabled and has a fixed exception priority of -1. The default name for the Hard Fault exception handler (as defined in CMSIS-Core) void HardFault_Handler(void); HardFault handler can use this register to determine whether a HardFault is caused by any of the configurable faults. Each fault indication status bit 1)be set when the fault occurs, 2)stay high until a value of 1 is written to the register.

27. 01 5. Debug fault status register (DFSR) Unlike other fault status registers, the DFSR is intended to be used by debug tools such as a debugger software or a debug agent software. Each fault indication status bit 1)be set when the fault occurs, 2)stay high until a value of 1 is written to the register.

28. 01 6. Fault address registers MMFAR and BFAR When a MemManage fault or a bus fault occurs, you might be able to determine the address of the transfer that triggered the fault using MMFAR or BFAR registers. Inside the Cortex-M3 and Cortex-M4 processors, the MMFAR and BFAR shared the same physical hardware.  Only one of the MMARVALID or BFARVALID can be 1 at a time. To ensure that the fault handlers are getting the accurate fault address information, 1.First read the value of MMFAR, or BFAR. 2. If they are still 1, then the fault address is valid.

29. 01 7. Auxiliary fault status register The AFSR was added from Cortex-M3 r2p0 onwards. Each fault indication status bit 1)be set when the fault occurs, 2)stay high until a value of 1 is written to the register. When a fault event happens in one of these devices, it triggers an interrupt, and the interrupt handler can use the AFSR to determine which device generated the fault. Next

30. 02 Analyzing faults The information (What went wrong) 1) be provided by the fault status registers and fault address registers 2) be obtained using various techniques and tools including: Stack Trace: trace the stacked register values including the stacked Program Counter (PC) from the stack pointers. Event Trace: If a program failure is related to exception handling, the event trace feature allows you to see which exceptions occurred before the failure and hence make it easier to locate the issue. Instruction Trace: Use the Embedded Trace Macrocell (ETM) to collect information about instruction executed, and display it on a debugger to identify the processor operations before the failure. Next

31. 03 Faults related to exception handling Faults can be generated during exception handling. The most common case is incorrect stack setup. 1. Stacking During exception entry, a number of registers are pushed to the stack. 2. Unstacking During exception exits, the processor restores register values by reading back values from the stack frame. If an MPU violation is detected, / If a bus error is received,

32. 03 Faults related to exception handling 3. Lazy stacking For the Cortex-M4 processor with floating point unit, Bus Fault and MemManage Fault could be triggered during lazy stacking. The lazy stacking feature allows the stacking of floating point registers to be deferred, and only push those registers to the allocated space if the exception handler uses the floating point unit. If a MPU access violation occurs, / If a bus error is received,

33. 4. Vector fetches If a bus error takes place during a vector fetch, the HardFault exception will be triggered, and the error will be indicated by the VECTTBL (bit 1) of the Hard Fault Status Register. 5. Invalid returns If the EXC_RETURN value is invalid or does not match the state of the processor, it will trigger a Usage Fault. 03 Faults related to exception handling

34. 04 Lockup 1. What is lockup? Lockup can happen if: A fault occurs during execution (in the HardFault or NMI exception handler) A bus error occurs during vector fetch (,, ) Trying to execute SVC instruction (,, ) Vector fetch at startup sequence During lockup, the processor stops program execution and asserts an output signal called LOCKUP. 2. Avoiding lockup In some applications, it is important to avoid lockup, and extra care is needed when developing the HardFault handler and NMI handler. One approach for developing HardFault and NMI handlers is to carry out only the essential tasks inside the handlers, and the rest of the tasks, such as error reporting, can be pended using a separate exception such as PendSV. Next

35. 05 Fault handlers 1.HardFault handler for debug purposes One of the common ways to report information about the fault is to create a HardFault handler that: Reports that the HardFault happened Reports the Fault Status Register and Fault Address Register values Reports additional information from the stack frame 2.Fault mask In a configurable fault handler, if needed we can set the FAULTMASK to: Disable all interrupts Disable/Enable the configurable fault handler

36. 06 Additional information 1. Running a system with two stacks For systems without an embedded OS, the two-stack arrangement can have another usage. => we need to get the Thread mode code to switch from using the MSP to using the PSP. 2.Detect stack overflow One of the common causes for software failure is stack overflow. If there is a stack issue such as stack leak in the software, the compilation report file cannot help you. So we need some ways to detect stack usage. Two methods 1.When the stack is fully used, to locate the stack near to the bottom of the SRAM space. 2.When the stack overflows, to use the MPU to define a small, inaccessible or read-only memory region at the end of the stack space. Next