1. Computer Architecture Chapter (5): Internal Memory
Eng. Nader Taleb

2. Semiconductor Main Memory
The basic element of a semiconductor memory is the memory cell. Its main properties are:
They exhibit two stable states (1 and 0).
They are capable of being written to set the state.
They are capable of being read to sense the state.

3. Semiconductor Memory Type
Read/Write easily and rapidly.
Volatile.
Temporary storage.
Static or dynamic.
RAM

4. Dynamic RAM (DRAM) Bits stored as charge in capacitors.
Charges leak, so it need refreshing even when powered.
Simpler construction and less expensive
Slower.
Require refresher circuit.
Essentially an analog device.
Level of charge determines value.
** It used in main memory.
Dynamic

5. DRAM Operation Address line active when bit read or written.
Transistor switch closed (current flows).
Write
Voltage to bit line (High for 1 low for 0).
Then signal address line (Transfers charge to capacitor).
Read
Address line selected (transistor turns on).
Charge from capacitor fed via bit line to sense amplifier
(Compares with reference value to determine 0 or 1).
Capacitor charge must be restored.

6. Static RAM (SRAM)
Bits stored as on/off switches (use traditional F-F logic gate).
No charges to leak.
No refreshing needed when powered.
More complex construction.
Larger per bit.
More expensive.
Faster.
It considered digital circuit.
Uses flip-flops.
** It used in cache memory.

7. SRAM Operation Transistor arrangement gives stable logic state.
C1 high, C2 low.
T1-T4 off, T2-T3 on.
State 0
C2 high, C1 low.
T2-T3 off, T1-T4 on.
Address line transistors (T5-T6) is switch.
Write – apply value to B & compliment to B.
Read – value is on line B.

8. Read Only Memory (ROM) It is permanent storage memory (Nonvolatile).
Benefits:
- Microprogramming.
- Library subroutines.
- Systems programs (BIOS).
- Function tables.
Data in ROM written during manufacture.
Very expensive for small runs.

9. Types of ROM Programmable (PROM) Written into only once.
Needs special equipment to program.
Read “mostly” memory.
Erasable Programmable (EPROM)
Like PROM but it read and write electrically.
Erased by UV through a window in the memory chip.
Electrically Erasable (EEPROM)
Can be written into it without erasing prior contents; only addressed are updated.
Takes much longer to write than read.
Flash memory.
Intermediate in both cost and functionality.

10. Chip Organization
A 16Mbit chip can be organized as 1M of 16 bit words.
A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on.
The elements of the array are connected by both horizontal (row) and vertical (column) lines. Each horizontal line connect to the Select terminal of each cell in its row; each vertical line connects to the Data-In/Sense terminal of each cell in its column.
A 16Mbit chip can be organized as a 2048 x 2048 x 4bit array.
Multiplex row address and column address.
11 pins to address (2 =2048).
Adding one more pin doubles range of values so x capacity. 11

11. Typical 16 Mb DRAM (4M x 4) Refresh circuit on chip. Disable chip.
Count through rows.
Read & Write back.

12. Packaging The address of the word being accessed. (A0–A~).
The data to be read out, consisting of 8 lines (D0–D~).
A chip enable (CE) pin. the CE pin is used to indicate whether or not the address is valid for this chip.
A ground pin
The power supply
A program voltage (Write)

13. 256 kB Module Organization

14. Detected using Hamming error correcting code.
Error Correction
Hard Failure.
Permanent defect.
Soft Error.
Random, non-destructive.
No permanent damage to memory.
Detected using Hamming error correcting code.

15. Advanced DRAM Organization
Basic DRAM same since first RAM chips.
Enhanced DRAM.
Cache DRAM.
In recent years, a number of enhancements to the basic DRAM architecture have been explored which are SDRAM, DDR-DRAM, and RDRAM.

16. Synchronous DRAM (SDRAM)
Access is synchronized with an external clock.
Address is presented to RAM.
RAM finds data (CPU waits in conventional DRAM).
Since SDRAM moves data in time with system clock, CPU knows when data will be ready.
CPU does not have to wait, it can do something else.
Burst mode allows SDRAM to set up stream of data and fire it out in block.
DDR-SDRAM sends data twice per clock cycle (leading & trailing edge).

17. (SDRAM)

18. SDRAM Read Timing

19. RAMBUS Adopted by Intel for Pentium & Itanium.
Main competitor to SDRAM.
Vertical package – all pins on one side.
Data exchange over 28 wires < cm long.
Bus addresses up to 320 RDRAM chips at 1.6Gbps.
Asynchronous block protocol. (480 ns access time).

20. DDR SDRAM Read Timing SDRAM can only send data once per clock.
Double-data-rate SDRAM can send data twice per clock cycle.
Rising edge and falling edge.
Read Timing

21. Cache DRAM
Mitsubishi.
Integrates small SRAM cache (16 kb) onto generic DRAM chip.
Used as true cache.
64-bit lines.
Effective for ordinary random access.
Used as a buffer to support serial access of block of data.
E.g. refresh bit-mapped screen.
CDRAM can prefetch data from DRAM into SRAM buffer.
Subsequent accesses solely to SRAM.

22. H.W (3)
4.1
4.2
4.8
4.12
Deadline: Tuesday,

23. Thank you