1. WEEK #12 Rapid Prototyping with FPGA EMT 351 Digital IC Design

2. INTRODUCTION TO FPGA Acronym for Field Programmable Gate Array FPGAs are programmable semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects FPGAs can be programmed to the desired application or functionality requirements (opposite to Application Specific Integrated Circuits (ASICs) where the device is custom built for the particular design) Although one-time programmable (OTP) FPGAs are available, the dominant type are SRAM based which can be reprogrammed as the design evolves (changes)

3. FPGA HISTORY ’47: Shockley, et. al. introduce first transistor at Bell Labs ’50: Bipolar junction transistor (BJT) introduced ’62: Hofstein, et. al. introduce metal-oxide semiconductor field-effect transistor (MOSFET) at RCA ’58: Jack Kilby introduced the integrated circuit ’70: Intel introduced 1024-bit DRAM, Fairchild introduced 256-bit SRAM ’71: Intel introduced first microprocessor, 4004 ’70: PLDs introduced, later CPLDs Xilinx introduced first FPGA in ’84, but engineers didn’t embrace them until early ’90s.

4. FPGA HISTORY – PLDs Early programmable logic device (PLD) offers programmable arrays to implement 2- level logic in sum-of-product (SOP) form Hierarchy of PLDs

5. Pre-wired AND array & programmable OR array PROMs were originally intended for use as computer memories to store programs and constant data However, engineers used them to implement lookup tables and state machines PROMs can be used to implement any block of combinational logic An important limitation of PROM is that the AND plane produces all products whether they are used or not  limits the number of inputs. FPGA HISTORY – PLDs (PROMs)

7. Programmable Logic Arrays (PLAs) allowed both the AND and OR plane to be programmed Number of AND functions in the AND array in independent of the number of inputs to the device Product terms can be shared among output functions The programmable links slow signals -- thus PLAs are slower then PROMs PLAs never achieved any significant level of market presence FPGA HISTORY – PLDs (PLAs)

8. Structure of PLA

9. Programmable Array Logic (PALs) were introduced in late 70’s to address speed problem of PLAs The AND array is programmable and the OR array is predefined, therefore they are faster than PLAs However, PALs only allow a restricted number of product terms to be OR’ed, at least on chip Real devices have many more inputs and outputs plus a variety of options available including: –The ability to invert the outputs –The ability to tristate the outputs –The ability to latch the outputs –The ability to configure certain pins as input or output FPGA HISTORY – PLDs (PALs)

10. Structure of PAL

11. In ’84, Altera introduced a CPLD based on a combination of CMOS and EPROM technologies CMOS allowed low power and high density while EPROM enabled these devices to be used for development and prototyping Altera’s real contribution was to use an interconnection array with less than 100% connectivity This increased complexity of software but keep the device scalable in terms of speed, power and cost Interconnection matrix usually has more wires than the individual SPLD blocks  a MUX is used to connect them. The programmable switches may be EPROM, EEPROM, FLASH or SRAM based. FPGA HISTORY – CPLDs

12. A generic CPLD structure typically consists of several SPLD blocks sharing a common programmable interconnection matrix Both the SPLDs and the interconnect can be programmed FPGA HISTORY – CPLDs

13. In early ’80s, a gap emerged in the digital IC continuum (field) At one end, SPLDs and CPLDs provided high configurability, fast design and modification times, but supported only small to moderate functions At the other end, ASICs supported large complex designs but were immutable once fabricated, expensive and time-consuming to design FPGA HISTORY – Early FPGAs Xilinx developed and made available in ’84 a new class of IC called the FPGA to fill the gap

14. The first FPGAs were based on CMOS and used SRAM cells for configuration The early chips used an array of programmable logic blocks (PLBs), which comprised a 3-input lookup table (LUT), a register and a MUX Each PLB can be programmed individually to perform an unique function The FF can be triggered by a positive or negative-going clock MUX allows selection of the LUT output or an external input PLB FPGA HISTORY – Early FPGAs The LUT can implement any 3- input logic function

15. Early FPGA Architecture FPGA HISTORY – Early FPGAs

16. FPGA TECHNOLOGIES Types of FPGA Anti-fused -based EPROM -based SRAM -based

17. programmed off-lineAntifuse-based FPGAs are programmed off-line using a special chip programmer Advantages non- volatile –Configuration is retained during power cycle (non- volatile). –They don’t require an external memory to store their configuration data, which saves on board cost and real estate Disadvantage –One-time-programming (OTP) –One-time-programming (OTP)  Not much use in development and prototyping environments FPGA TECHNOLOGIES – Anti-fused-based

18. rad hardTheir interconnect structure is "rad hard", or relatively immune to the effects of radiation the configuration data is buried deep inside them Unfortunately, the technology used to fabricate anti-fuse FPGAs is one or more generations behind the technology used for SRAM versions FPGA TECHNOLOGIES – Anti-fused-based

19. Configuration cells are connected together in a long shift-register-style chain (scan chain) Programmingoff-linesomein- system programmingProgramming done off-line, some allow in- system programming (ISP) Use charged floating gates, programmed by a high voltage Reprogrammablenon-volatileReprogrammable & non-volatile longer programming timeProgramming time is about 3 times longer than SRAM version (longer programming time) FPGA TECHNOLOGIES – EPROM-based

20. high static powerHave high static power because of the internal pull-up resistors For security, some use a multibit key (50 to several hundred bits) Disadvantage –The devices require about 5 additional process steps beyond the standard CMOS process –Similar to antifuse, this causes a lag of these devices, technology wise FPGA TECHNOLOGIES – EPROM-based

21. CMOS transmission gatesMainly uses CMOS transmission gates to establish interconnect Status of the gatescontentsStatus of the gates is determined by contents of SRAM configuration memory fast reconfigurationThe majority use SRAM based configuration cells, which allows fast reconfiguration –Allows new design ideas to be quickly implemented and tested –Allows evolving standards and protocols to be accommodated –Allows the FPGA to carry out multiple functions, such as self-test or board/system test at power- up and something else later FPGA TECHNOLOGIES – SRAM-based

22. very heavily invested inAnother advantage - SRAM technology is very heavily invested in, and therefore, FPGA companies can leverage this –The same process used to fabricate the logic gates on the FPGA is used to fabricate SRAM  no special processing steps are needed Disadvantage volatility external memorymicroprocessor –In terms of volatility, which is overcome with a special external memory device or microprocessor (costly either way) difficult to protectintellectual property –Can be difficult to protect your intellectual property  the configuration file maybe somewhere on disk, in memory, etc  SOLUTION: use bitstream encryption FPGA TECHNOLOGIES – SRAM-based

23. Comparison between types of FPGA

24. THE CURRENT FPGA STRUCTURE Basic FPGA Architecture I/O Block Configurable Logic Blocks Digital Clock Management Interconnect Memory

25. FPGA STRUCTURE – Common Features Configurable Logic Block (CLBs) –Basic logic unit in an FPGA –Exact numbers and features vary from device to device, but every CLB consists of a configurable switch matrix with 4 or 6 inputs, some selection circuitry (MUX, etc), and flip-flops –The switch matrix is highly flexible and can be configured to handle combinatorial logic, shift registers, or RAM Inner structure of CLB

26. SelectIO (IOBs) –Provides the ideal interface bridge in the system –Grouped in banks with each bank independently able to support different I/O standards –Today’s leading FPGAs provide over a dozen I/O banks, thus allowing flexibility in I/O support FPGA STRUCTURE – Common Features Inner structure of IOB

27. Interconnect –Flexible interconnect routing routes the signals between CLBs and to and from I/Os –Various types of routing; from that designed to interconnect between CLBs to fast horizontal and vertical long lines spanning the device to global low-skew routing for Clocking and other global signals –Design software makes the interconnect routing task hidden to the user unless specified otherwise, thus significantly reducing design complexity. FPGA STRUCTURE – Common Features

28. Memory –Embedded Block RAM memory is available in most FPGAs –Allows for on-chip memory for your design Digital Clock Management –Provided by most FPGAs in the industry –The most advanced FPGAs from Xilinx offer both digital clock management and phase-looped locking that provide precision clock synthesis combined with jitter reduction and filtering FPGA STRUCTURE – Common Features

29. FPGA STRUCTURE – Altera Stratix II

30. FPGAs vs. ASICs – Design Advantages FPGA & ASIC Design Advantages FPGA Design AdvantagesASIC Design Advantages Faster time-to-market - no layout, masks or other manufacturing steps are needed Full custom capability - for design since device is manufactured to design specs No upfront NRE (non recurring expenses) - costs typically associated with an ASIC design Lower unit costs - for very high volume designs Simpler design cycle - due to software that handles much of the routing, placement, and timing Smaller form factor - since device is manufactured to design specs More predictable project cycle - due to elimination of potential re-spins, wafer capacities, etc. Higher raw internal clock speeds Field reprogramability - a new bitstream can be uploaded remotely

31. FPGAs vs. ASICs – Design Flow FPGA vs. ASICs Flow Design Comparison

32. RAPID PROTOTYPING WITH VERILOG & FPGA Definition –Create a working prototype as quickly as possible using FPGA with Verilog as the design entry Advantages –It bypass the structural detail that is forced by schematic-based entry method –Allows usage of single clock  timing-driven routing tools works more efficient –FPGA is register-rich  recommended to employ one-hot encoding in state machines  produce simpler NS & output logic

33. RAPID PROTOTYPING WITH VERILOG & FPGA