1. CMOS Analog 집적회로 설계
전북대학교 방 준 호

2. 1. 기본 증폭 회로 해석

3. (1) The real world is analog !
1.Analog IC 및 MOS Technology Trends 1
1. Analog IC 및 MOS Technology Trends
(1) The real world is analog !
Hearing
Speaking
Data
Processing
blocks
Analog
circuits

4. MOS Technology Trends

5. MOS Technology Trends

6. Analog IC designs will never go away because
MOS Technology Trends 2
Analog IC designs will never go away because
as end (natural) signal are analog, analog front ends are
essential (amplifier, filters, ADCs and DACs)
radio transmission and reception is an analog task
analog is faster than digital for some applications
as speeds go up, digital signals must be treated as analog
SOC (system on chip) trends to make the analog designs more
important than ever.

7. MOS Technology Trends Lilienfeld U.S. patents
1930: “Method and apparatus for controlling electric currents”,
1933: “Device for controlling electric current”

8. 1940: Ohl develops the PN Junction
MOS Technology Trends
1940: Ohl develops the PN Junction
1947: Bardeen and Brattain create point contact transistor
1951: Shockley develops a junction transistor manufacturable in quantity
When Noyes came to MIT, much to his surprise, few people had even heard about the transistor
Point contact transistor
Shockley develops a junction transistor

9. Jack Kilby integrated circuit
MOS Technology Trends
1959: Jack Kilby, working at TI, dreams up the idea of a monolithic “integrated circuit”
Components connected by hand-soldered wires and isolated by “shaping”, PN-diodes used as resistors
1961: TI and Fairchild introduce the first logic ICs
1962: RCA develops the first MOS transistor
RCA 16-transistor MOSFET IC
Fairchild bipolar RTL Flip-Flop
Jack Kilby integrated circuit

10. Fairchild micromosaic IC
MOS Technology Trends
1967: Fairchild develops the “Micromosaic” IC using CAD
1970: Fairchild introduces 256-bit Static RAMs
1970: Intel starts selling1K-bit Dynamic RAMs
Intel K-bit DRAM
Fairchild micromosaic IC
Fairchild bit SRAM

11. Number of Transistors 80x86 Processors
MOS Technology Trends
1971: Intel introduces the Microprocessor
Moore’s Law
Number of Transistors 80x86 Processors
4004
8086
80286
80386
80486 P5
(Pentium) P6
(Pentium Pro)
Pentium II
Merced
Doubling every 1.9 year
2.75 year

12. Supply Voltage: Vdd Cut-off frequency 2012 today today
MOS Technology Trends
Supply Voltage: Vdd
today
2012
Cut-off frequency
today
VDD is a measure for the low-voltage
low- power consumptions
ft is a measure for the speed
of (analog) circuits

13. Interconnect: > 6 metal layers
MOS Technology Trends
Interconnect: > 6 metal layers
30 nm Devices [Intel]
mass production in 2009
Transistor gate length 70 nm
Metal-1 width 180 nm
30 nm physical gate length
0.8 nm conventional SiO2(N)

14. MOS Technology Trends
Manufacture of VLSI

15. Wafer Fabrication Process
MOS Technology Trends
Wafer Fabrication Process

16. ADSL Analog Front-end Filter 설계 과정 예
MOS Technology Trends 3
ADSL Analog Front-end Filter 설계 과정 예
1. 시스템 Spec.검토
ANSI의 표준화 규격
(T :DMT방식)
Analog Front-end
회 로
구 조 및 특 성
수신 단 (Rx)
Transconductor
3.3V, －1.2 ~ ＋1.2 Input linearity
Low-pass Filter
3rd-Elliptic, 1.1MHz, Gm-C
High-pass Filter
3rd-Butterworth, 138kHz, Gm-C
Σ-Δ ADC (Modulator)
12bit, 1MHz(50MHz), Cascade 2-2
AGC1(AGC2)
0㏈-31㏈, 5bit DAC control
ADC Amplifier
80dB, 315MHz, Folded Cacode(CMFB)
ADC Comparator
50㎒)
송신 단 (Tx)
Line-driver(LD)
98 dB, 15MHz, Fully-Differential
Pre-driver(PD)
-15㏈-0㏈, 4bit DAC control,
3rd-Elliptic, 138kHz, Gm-C
Σ-Δ DAC (Demodulator)
12 bit at 1MHz/s, 50Msampling, 4th SSSB
DAC Interpolator Filter
141tap, 24bit
DC Bias Circuit
온도변화에 적응하는 전압 및 전류원
Non-overlaping Clock Generator
3.3ns Non-overlaping time, 1.6ns delay
부가 회로
CMOS Switching Circuit
ON resistance 370[Ω]

17. 2. 설계 사양에 따른 설계 방법과 구조결정 4 (1) 설계 사양 (2) 함수 결정 (3) 능동필터 모의 방법 결정
MOS Technology Trends 4
2. 설계 사양에 따른 설계 방법과 구조결정
(1) 설계 사양
<Tx의 저역 필터 (LPF : 138 ㎑) 설계>
<Rx의 저역 필터 (LPF : 1.1 ㎑) 설계>
(2) 함수 결정
설계 사양을 만족하기 위한 필터함수 결정 i V V o
<3차 타원 저역필터>
<3차 바터워스 저역필터>
(3) 능동필터 모의 방법 결정
Gyrator 직접모의법
Biquad 실현법
SFG (signal flow graph) 모의법 
필터의 감도 특성이 우수한 장점
Iksan National College

18. MOS Technology Trends 5
3. 회로 설계
(1) Passive Filter
(2) Active Filter

19. MOS Technology Trends 6
4. 시뮬레이션 (HSPICE)

20. MOS Technology Trends 7
5. Layout 및 Chip제작
(1) Layout
(2) Fabrication

23. 6. Chip Test 8 (1) Pin block (2) Test MOS Technology Trends Tx AGC
LF 138kHz
4-order
DAC
-15~0dB Rx
LF 1.1MHz
0~30dB
Sigma-Delta
ADC
MUX
Selector
External
Input
Internal
Signal
ex_clk vc
vcm
vrefp
vrefn up un
Gain
Control
Tx_G1
Tx_G2
Rx_G2
Rx_G1
Tx_out+
Tx_out-
Rx_in+
Rx_in-
Tx_Agcin+
Tx_Agcin-
Tx_Ftout+
Tx_Ftout-
Tx_Ftin+
Tx_Ftin-
Rx_Ftout+
Rx_Ftout-
Rx_Agcin+
Rx_Agcin-
Rx_Agcout+
Rx_Agcout- Vb
VDD_DAC
VSS_DAC
VDD_ADC
VSS_ADC
VDD_Tx
VSS_Tx
VDD_Rx
VSS_Rx
(1) Pin block
(2) Test

24. n Overview of CMOS Fabrication SiO2 V out V DD GND V in n,100 Si
MOS Technology Trends
Overview of CMOS Fabrication
V out
V in
V DD
GND
n,100 Si
Substrate n
SiO2
(a) Oxidation

25. (C) Boron p-well diffusion, Deep drive-in
MOS Technology Trends n PR
SiO2 n
SiO2 p
(b) Pattern, etch
p-well
(C) Boron p-well diffusion,
Deep drive-in
SiO2 p n
(d) p-channel source & drain pattern
SiO2 p n P+
(e) Boron p+ diffusion

26. (f) n-channel source & drain pattern
MOS Technology Trends
SiO2 p n P+
(f) n-channel source & drain pattern
SiO2 p n P+ n+
(g) Phosphorus n+ diffusion
SiO2 p n P+
p-channel n+
n-channel
(h) Gate oxide pattern

27. (j) Open contact windows
MOS Technology Trends
SiO2 p n P+ n+
(i) Gate oxide growth
SiO2 p n P+ n+
(j) Open contact windows
SiO2 p n P+ n+
(k) Metalize and pattern

28. 2. MOS Transistor의 기초 (1) MOS Transistor의 물리적 구조 9
nMOS
pMOS
Poly-Si
Poly-Si
SiO2
SiO2 n+ n+ p+ p+
n-well
P-sub
p-sub L L n+ W p+ W
gate(G)
gate(G)
source(S)
drain(D)
drain(D)
source(S)
bulk(B)
bulk(B)

29. (2) MOS Transistor의 Basic Operations (nMOS)10
(2) MOS Transistor의 Basic Operations (nMOS)
Cutoff n+
P-sub
+++++ S G D B
Linear(triode) n+
P-sub S G D B
channel
depletion region
Saturation G S D n+ n+
P-sub B
VGS < VTH
VGS > VTH
VGS > VTH
VGD < VTH
VGD > VTH
VGD < VTH
VDS < VGS- VTH.
VDS > VGS- VTH.
IDS = b [(VGS-VTH) VDS VDS2 ] 1 2
IDS = 0 b 2
IDS = (VGS- VTH)2
b = m Cox = m W L
eo eox
t ox

30. (3) Body Effect 11 2. MOS Transistor의 기초 G G S D S D n+ n+ n+ n+
depletion
region
IVBS1I < IVBS2I
P-sub
P-sub B B
VTH = VTH0 + g ( IFsI - VBS - IFsI )
VTH0 = VTH ( when VBS = 0 )
g : body effect parameter
= 2 esi qNA / Cox

31. (4) Channel-Length Modulation Effect
2. MOS Transistor의 기초 12
(4) Channel-Length Modulation Effect
IVDS1I < IVDS2I G G S D S D n+ n+ n+ xd n+
depletion
region
P-sub
P-sub B B 1 2 W
Leff 1 2 W
L-xd
IDS = mnCox (VGS- VTH)2
= mnCox (VGS- VTH)2 1 2 W L
= mnCox (VGS- VTH)2 (1 + lVDS)
l : channel-length modulation parameter 1 L xd
VDS
l =

32. (5) MOSFET I-V Curves 13 IDS - VDS IDS - VGS 2. MOS Transistor의 기초 IDS
linear
saturation
linear
saturation
l = 0
l = 0
VGS
VDS
VDS
IDS - VDS
(IDS)1/2
cutoff
on(saturation)
(IDS)1/2
IVBSI
VGS
VGS
VTH
VTH0
VTH(VBS)
IDS - VGS

33. (6) MOSFET Drain-source Current Summary
2. MOS Transistor의 기초 14
(6) MOSFET Drain-source Current Summary
nMOSFET
(VTHn > 0) D
Cutoff
IDS = 0
IDS = bn [ (VGS-VTHn)VDS VDS2 ] 1 2
IDS G B
Linear bn 2
Saturation
IDS = (VGS- VTHn)2 (1 + ln VDS) S
pMOSFET
(VTHp < 0) S
Cutoff
ISD = 0
ISD = bp [ (VSG-VTHp)VSD VSD2 ] 1 2
IDS
Linear G B bp 2
Saturation
ISD = (VSG- VTHp)2 (1 + lp VSD) D

34. 15 실습 문제 2-1 : Bias point 계산 2. MOS Transistor의 기초 VDD=+5V
VTH0 = 0.8 V
VTH = VTH0 + g ( IFsI - VBS - IFsI )
g = V
RB =10kW
= V
Ifs I = 0.7 V VR
VBS = - 3 V M1
mnCox = mA/V2
b1 = mnCox(W/L) = 533 mA/V2
W/L = 20mm /2.0mm
VSS=-2V
VBB=-5V
M1 in saturation
IRB = IM1
VDD-VR 1 2 1 2
= b1 (VGS1- VTH1)2
= b1 (VR- VSS - VTH1)2 RB
VR = V or V
IRB = IM1 = mA

35. 실습 문제 2-2 : Bias Level Shifter의 Bias point 계산
2. MOS Transistor의 기초 16
실습 문제 2-2 : Bias Level Shifter의 Bias point 계산
VDD=+5V
VTH0 = 0.8 V
VINQ=? M2
R1=30kW
g = V
Ifs I = 0.7 V
mnCox = 20 mA/V2
VOUTQ
(W/L)1 = 30mm /2.0mm M1
(W/L)2 = 20mm /2.0mm
R2=20kW
VDD= 0V
Bias Level Shifter회로의 출력전압 (VOUTQ)을 2.5V 로 얻어내기 위하여 VINQ에 몇 V를 인가하여야 하는가 ?
(단. 모든 MOS는 Saturation에서 동작하며 Channel length 효과는 무시함.)

36. VOUT = f (VIN) : Nonlinear function (비선형 함수)
3.Small-Signal Analysis 17
3. Small-Signal Analysis
(1) Nonlinear operations
VIN
f()
VOUT = f (VIN) : Nonlinear function (비선형 함수)
VOUT
VOUT
transfer curve
Nonlinear transfer curve
계산이 복잡
VIN t
Linear 모델 필요
VIN t

37. (2) Linearization of Nonlinear operations
3.Small-Signal Analysis 18
(2) Linearization of Nonlinear operations
VIN = VINQ Vin
VOUT = VOUTQ + Vout
f()
VOUT
transfer curve
VOUT = VOUTQ + Vout
AV * Vin = Vout
VOUTQ + AVi * Vin
AV = dVout/dVin IQ
VOUTQ
그래프의 기울기
= 전압의 증폭도
VIN=VINQ+ Vin t
VIN
VINQ
Vin
VINQ t t t
Vin
bias (Q)
small-signal
입력과 출력 신호들은 두개의 성분, bias(Q)와 small-signal 신호를 가진다.
small-signal model linear operations,
small-signal parameters depend on bias point

38. = back-gate transconductance
3.Small-Signal Analysis 19
(3) MOSFET의 Small-signal model (Low-frequency)
IDS = IDSQ + DIDS = IDS (VGS, VDS, VBS ,)
VGS = VGSQ + DVGS
VDS = VDSQ + DVDS
VBS = VBSQ + DVBS
IDS
VGS Q
DVGS
IDS
VDS Q
DVDS
IDS
VBS Q
DVBS
IDS = + + gm
IDS =
DVGS go
DVDS
gmb + +
DVBS gm
= transconductance gm
IDS =
= b (VGSQ- VTH) (1 + l VDSQ) = 2b IDSQ (1 + l VDSQ) = 2b IDSQ
VGS Q go
= output conductance gO
IDS 1 2
l IDSQ
1 + l IDSQ 1 ro =
= b (VGSQ- VTH)2 l = = l IDSQ =
VDS Q
gmb
= back-gate transconductance
gmb
IDS
IDS
VTH = = = gm g =
hgm
VBS Q
VTH
VBS Q
IFI-VBSQ gm
>> gmb
>> go

39. (4) Small-signal 등가회로 (1)
3.Small-Signal Analysis 20
(4) Small-signal 등가회로 (1)
VDD RL
vO = VO + vo M
VGS io
vi = vgs vI
vI = VGS + vgs
vO = VO + vo
(1) 소신호 성분 무시 할 때 1 2 W L
IO = mnCox (VGS - VTH)2
( if, l = 0 )
VDD - VO RL
IO = 1 2 W L
VO = VDD -
mnCox (VGS - VTH)2 RL
(2) 소신호 성분 포함 할 때 1 2 W L
iO = mnCox (VGS + vgs - VTH)2
( if, l = 0 )
VDD - (VO + vo) RL
iO =
vgs W L 2
vo = - RL
mnCox { (VGS - VTH) vgs } 2
vgs 2
에 의한 왜곡율 10% 이내 조건

40. (4) Small-signal 등가회로 (2)
3.Small-Signal Analysis 21
(4) Small-signal 등가회로 (2)
IvgsI
< 0.2 (VGS - VTH)
조건을 만족한다면 W L
vo = - RL
mnCox { (VGS - VTH) vgs }
vo = - RL io 이므로
io =
mnCox (VGS - VTH) vgs W L
VDD RL vo M io vi gm
Body effect 무시한 등가회로 RL
vin
vgs + - G
gmvgs D B S
vout ro G D B S is rs
VB 전압 = 0 일때 RL
vin
vgs + - G
gmvgs
gmbvbs D B S
vout
ro=1/go ro
T형 등가회로

41. Direct(Nonlinear) Method Small-Signal (Linear) Analysis
3.Small-Signal Analysis 22
(5) Small-signal model 활용 예제
VDD=+5V
RL =100kW
VTH0 = 0.8 V
g = 0.41V
VTH = VTH0 + g ( IFsI - VBS - IFsI )
Ifs I = 0.7 V
VBS = 0 V
= 0.8 V
VOUT
VIN
mnCox = 53.3 mA/V2
l = V-1
b1 = mnCox(W/L) = 533 mA/V2 M1
W/L = 20mm /2.0mm
VSS=-5V
Input Signal
VIN = sin(wt) bias VINQ + small signal VIN
Direct(Nonlinear) Method
VDD-VOUT b1 2 b1 2
= (VGS1-VTH1)2 (1+l VDS)
= (VIN-VSS-VTH1)2 [1+l(Vout-VSS)] RL
(VIN-VSS -VTH1)2 (1+l VSS) - VDD/RL
b1/2
19.99[0.01sin(wt) + 0.2]2 -5
VOUT = =
= ?
b1/2
(VIN-VSS -VTH1)2 l + 1/RL
1.33[0.01sin(wt) + 0.2]2 +1
Small-Signal (Linear) Analysis b1 2
Bias
IQ= (VGSQ-VTH1)2 = 10.7mA VOUTQ= VDD-IQRL= 3.93V gm go
= 2b1 IQ
= 106.8mA
= l IQ
= 0.54mA RL
vout G D
vin
by KCL
gm1vgs1+ gmb1vbs+ go1vout + vout/RL
0 =
gm1vgs1+ go1vout + vout/RL = +
vgs1
ro1=1/go1
vout
gm1
gm1vgs1
gmb1vbs1
AV =
= - =
vout = AV . vin
= sin(wt) -
vin
go1+1/RL S B
VOUT = VOUTQ + vout =
sin(wt)

42. CS(Common-Source Amp.)
4. Basic MOS Amplifiers & Small-Signal Analysis 23
4. Basic MOS Amplifiers & Small-Signal Analysis
(1) Basic MOS Amplifiers
CS(Common-Source Amp.)
CG(Common-Gate Amp.)
CD(Common-Drain Amp.)
VDD RL
vout
vin
VSS D G S
VDD RL
vout
VGG
VSS D G S
vin
VDD RL
vout
VBB D G S
vin
VSS 구 조
Input
gate - source
source - gate
gate - drain
Output
drain - source
drain - gate
source - drain

43. (2-1) 저항부하를 갖는 CS Amplifier
4. Basic MOS Amplifiers & Small-Signal Analysis 24
(2) CS Amplifiers의 Small-Signal Analysis
(2-1) 저항부하를 갖는 CS Amplifier
VDD RL
vout
vin
VSS D G S RL
vout G D
vin +
vgs
gmvgs
gmbvbs
ro=1/go - S B
vout
전압 이득 (Voltage Gain) :
AV =
vin
By vout - node
gmvgs+ gmbvbs+ govout + vout/RL
0 =
gmvgs+ govout + vout/RL =
vout gm gm
AV =
= -
= - =
- gm (ro II RL)
- gmro =
vin
go+1/RL
1/ro +1/RL
2m Cox
W/L ID l
- gmro = -

44. (2-2) Ideal DC 전류원 부하를 갖는 CS Amplifier
4. Basic MOS Amplifiers & Small-Signal Analysis 25
(2-2) Ideal DC 전류원 부하를 갖는 CS Amplifier
VDD M
vout
vin ID
vout G D
vin +
vgs
gmvgs
gmbvbs
ro=1/go - S B
vout
전압 이득 (Voltage Gain) :
AV =
vin
By vout - node
gmvgs+ gmbvbs+ govout
0 =
gmvgs+ govout =
vout gm gm
2m Cox
W/L ID l
AV =
= -
= -
- gm ro = = -
vin go
1/ro l
는 L 에 반비례 하므로 WL ID AV
전압이득이 Bias 전류 ID에 영향 받음

45. (2-3) MOS 다이오드를 부하로 사용하는 CS Amplifier
4. Basic MOS Amplifiers & Small-Signal Analysis 26
(2-3) MOS 다이오드를 부하로 사용하는 CS Amplifier
VDD M1
vout
vin M2 io
ro2=1/go2
gm2vgs2
gmb2vbs2
vout + vi
ro1
gm1vi -
전압 이득 (Voltage Gain) :
vout
gm1 ~
AV =
= -
vin
gm2 + gmb2 + 1/ro1 + 1/ro2
gm1
(W/L)1 ~
AV = -
= -
gm2
전압이득이 Bias 전류 ID와 무관하고
W/L에 의해 결정됨
(W/L)2
Load impedance 낮음  RC 시상수 작음  주파수 특성 우수  광대역 증폭기에 적합

46. (2-4) 전류미러(Current mirror) 를 부하로 사용하는 CS Amplifier
4. Basic MOS Amplifiers & Small-Signal Analysis 27
(2-4) 전류미러(Current mirror) 를 부하로 사용하는 CS Amplifier
VDD M1
vout M2 io M3 vi
소신호 등가회로
DC Bias 전류 = 0
vout + vi
gm1vi
ro1
ro2 -
vout
vin
AV =
gm1 (ro1 ll ro2 )
= - ~
(2-5) CMOS inverter형 CS Amplifier
VDD M1
vout M2 vi
gm2vi
ro2 +
vout vi
gm1vi -
ro1 ~
vout
AV =
= -
(gm1+ gm2 ) ( ro1 ll ro2 )
vin

47. (2-6) CS Amplifier 의 주파수 특성 (High frequency)
4. Basic MOS Amplifiers & Small-Signal Analysis 28
(2-6) CS Amplifier 의 주파수 특성 (High frequency) C A B A B
CGD
VDD +
vout vi CI ro ID
gm1vi -
Miller 정리
vout Rs
vin M1 +
vout vi CI
ro1
CGD
(1+gmro)
gm1vi CL 1 -
CGD
(1+ gmro)
CI= (CGS+CGB)
vout (s)
gm r o
AV (s) = =
vin (s)
(1+ s/wp1)
(1+ s/wp2) 1
wp1 =
Dominant pole (우수극점)  주파수 특성에 영향
Rs[ C1+ CGD (1+gmro) ] 1
wp2 =
Nondominant pole (비우수극점) 1
ro[ CL+ CGD (1+ gmro) ]

48. (3-1) 이상적인 전류원 부하를 갖는 CG Amplifier
4. Basic MOS Amplifiers & Small-Signal Analysis 29
(3) CG Amplifiers의 Small-Signal Analysis
(3-1) 이상적인 전류원 부하를 갖는 CG Amplifier
T형 등가회로
VDD + -
vout is vi rs ro
IDC
vout io
vout
gmvgs
gmbvbs
ro=1/go D
VGG G S
vin
vin
전압 이득 (Voltage Gain) : vi
is = -
= -
gm1 vi rs
vo = -
is ro + vi =
( gm1 ro + 1 ) vi
vout
AV = =
( gm1 ro + 1 )
vin
전압이득  1보다 조금 (+) 값

49. (3-2) 저항 부하를 갖는 CG Amplifier 입력 저항 (Input Resistance) :
4. Basic MOS Amplifiers & Small-Signal Analysis 30
(3-2) 저항 부하를 갖는 CG Amplifier
VDD RL
vout
VGG
VBB D G S
vin RL
vout G D +
vgs
gmvgs
gmbvbs
ro=1/go - S - + B ix vx vx
입력 저항 (Input Resistance) :
Rin = ix
By vx - node
Ix + gmvgs+ gmbvbs+ go(vout-vx)
0 = =
Ix + gm (0-vx) + gmb (0-vx) + go(vout-vx)
By vout - node
0 =
gmvgs+ gmbvbs+ go(vout-vx) + vout/RL =
gm (-vx) + gmb (-vx) + go(vout-vx) + vout/RL vx
1 + goRL
1 + goRL
Rin = = = ix
gm + gmb + go gm
출력 저항 RL이 0 일 때  입력저항 Rin 
 전류원 입력을 받고 전류를 출력하기에 적합
출력 저항 RL이 oo 일 때  입력저항 Rin 

50. (3-3) CG Amplifier 의 주파수 특성
4. Basic MOS Amplifiers & Small-Signal Analysis 31
(3-3) CG Amplifier 의 주파수 특성
VDD RL C2 RL D
vout
vout
gmvgs
gmbvbs ro D G G S S C1 Rs vi
CI= (CGS+CBS)
vin 1
C2= (CGD+CBD)
wp1 =
( Rs II Ri ) C1 1 1
wp1
Rs C1
gm+ gmb 1 Rs C1 1 1 =
Rs C1 Rs 2
WLCox
+ W CGSO
+ L CBS 3
우성극점의 크기가 CS Amplifier 에 비하여 크다  CG Amplifier 가 CS Amplifier 보다 주파수 특성 우수

51. (4) CD Amplifiers의 Small-Signal Analysis
4. Basic MOS Amplifiers & Small-Signal Analysis 32
(4) CD Amplifiers의 Small-Signal Analysis
(4-1) 이상적인 전류원 부하를 갖는 CD Amplifier
VDD D D G
vin G +
vin S ro
vout
gmvgs
gmbvbs -
IDC S
vout
전압 이득 (Voltage Gain) :
vgs = vi vo
vbs = vo
By KCL at node S
vout gm gm
AV = = = 1
vin
( gm gmb )
gm + gmb ro
전압이득  gmb 는 gm의 10내지 30% 이므로 전압 이득은 1보다 조금 작은 양 (+)의 수이다.

52. (4-2) 저항 부하를 가진 CD Amplifier 출력 저항 (Output Resistance) :
4. Basic MOS Amplifiers & Small-Signal Analysis 33
(4-2) 저항 부하를 가진 CD Amplifier
VDD D D
vin G b G
vin
VBB + S
vgs
gmvgs
gmbvbs
ro=1/go
vout - RL S B iy + RL
VSS vy - a
전압 이득 (Voltage Gain) :
vout gm
AV = =
vin
( gm gmb )
roII RL vy
출력 저항 (Output Resistance) :
Rout = iy
Vin 0
By vout - node a b
vy/RL + govy = iy + gmvgs+ gmbvbs
iy + gm (0-vy) + gmb (0-vy) = vy 1 1 1 1
Rin = = =
gm + 1/RL =
II RL gm = iy
gm + gmb + go + 1/RL gm

53. (4-3) CD Amplifier 의 주파수 특성 (High Frequency)
4. Basic MOS Amplifiers & Small-Signal Analysis 34
(4-3) CD Amplifier 의 주파수 특성 (High Frequency)
VDD RL
vout
VBB D G S
vin
VSS RS
CGD ro vs
CGS
gmvgs
gmbvbs
CGB vs RL CL 1
w-3dB(input) =
gmb Rs
CGD
+ CGB
+ CGS
gm + gmb ~
gm + gmb = CL
CD Amplifier 의 주파수 특성  CG Amplifier 과 CS Amplifier 보다 우수

54. 실습 문제 4-1 : CG Rs 삽입시 출력측에서 본 저항(Ro) 구하기
4. Basic MOS Amplifiers & Small-Signal Analysis 35
실습 문제 4-1 : CG Rs 삽입시 출력측에서 본 저항(Ro) 구하기
VDD RL
vout
vin
VGG
VBB RS Ro

55. 실습 문제 4-1 풀이 : CG Rs 삽입시 출력측에서 본 저항(Ro) 구하기
4. Basic MOS Amplifiers & Small-Signal Analysis 36
실습 문제 4-1 풀이 : CG Rs 삽입시 출력측에서 본 저항(Ro) 구하기
VDD RL
vout
vin
VGG
VBB RS Ro G
vout ix D +
vgs
gmvgs
gmbvbs + vx ro - - S VS RS

56. (5) Cascode Amplifiers의 Small-Signal Analysis
4. Basic MOS Amplifiers & Small-Signal Analysis 37
(5) Cascode Amplifiers의 Small-Signal Analysis
VDD RL
vout
vin
VSS
vGG M1 M2 CG CS RL
vout G2 D2 +
vgs2
ro2=1/go2
gm2vgs2
gmb2vbs2 - G1 va S2 D1
vin +
vgs1
ro1=1/go1
gm1vgs1
gmb1vbs1 - S1
B1, B2
By vout - node
ro1 Ro
ro2
vout -
gm2vgs2+ gmb2vbs2 + go2 (vout-va) = RL
gm2(-va) + gmb2(-va) + go2(vout-va) =
By va - node
vout -
gm1vgs1+ gmb1vbs1 + go1va =
gm1vin+ go1va = RL
CG 출력저항
vout
gm1RL
Av = = -
gm1[ RL II{gm2 (ro2 II RL ) ro1}] = -
vin
go1 (1+ go2RL ) 1+
gm2+ gmb2+ go2

57. (6) Differential Amplifiers의 Small-Signal Analysis
4. Basic MOS Amplifiers & Small-Signal Analysis 38
(6) Differential Amplifiers의 Small-Signal Analysis
(6-1) Differential signal와 Single ended signal (1)
Single ended signal +
vout
vin + - t -
Differential signal +
vout -
CM level
vin + - t t
vin + -

58. (6-1) Differential signal와 Single ended signal (2)
4. Basic MOS Amplifiers & Small-Signal Analysis 39
(6-1) Differential signal와 Single ended signal (2)
Differential signal advantage
High rejection of environmental noise
VDD RL
vo1
vi1 M1 M2
vo2
vi2
vout1
vin1
CM level
vin2
vout2 t
Differential signal disadvantage
Sensitive to input common mode level
Change in input CM level : change is bias I, Gm or clipping !
vout1
vin1
CM level
vin2
vout2 t

59. 4. Basic MOS Amplifiers & Small-Signal Analysis40
(6-2) Tail current
VDD
VDD RD RD RD RD
vo1
vo2
vo1
vo2
ID1
ID2
ID1
ID2 M1 M2 M1 M2
vi1
vi1
vi2
vi2
ISS
출력 공통모드 전압 (VoCM)이
입력 공통모드 전압 (ViCM)에
영향을 받는다.
VSS
Tail current 첨가

60. Assume M1 and M2 are identical41
(6-3) 저항성 부하를 갖는 NMOS 차동증폭기(1)
Small signal analysis
VDD RL
vo1 VB
VSS
vi1 M1 M3 M2
vo2
vi2
Iss I1 I2 vc RL RL G1 D1 D2 G2
vi1
vo1
v02
vi2 + +
vgs1
gm1vgs1
ro1
ro2
gm2vgs2
vgs2 VC - - S1 S2
ro3
Differential Signals
Dvi
vi1 - vi2
By vo1 - node =
vo1 - vc
vo1
Dvo
vo1 - vo2 = - RL (I1 - I2) = - RL DI =
gm1 (vi1 - vc) + +
= 0
ro1 RL
Current Equation
By v02- node
vo2
I1 = b/2 (vi1 - vc - VTH)2
vo2 - vc
gm2 (vi2 - vc) + +
= 0
ro2 RL
I2 = b/2 (vi2 - vc - VTH)2
2ISS
b/2
I1 + I2 = ISS
DI = I1 - I2 = b/2 Dvi Dvi2
Assume M1 and M2 are identical
Voltage Gain
Dvo DI
vo1 - vo2 Av = =
-RL
- RL GM = -
gm1(ro II RL)
gm1 RL
Av = = -
Dvi
Dvi =
Q:D vi =0
Q:D vi =0
vi1 - vi2
for ro >> RL DI GM = =
b ISS =
2b I1Q =
gm1(2)
Dvi
Q:D vi =0 Av =
- gm1 RL

61. (6-3) 저항성 부하를 갖는 NMOS 차동증폭기(2)
4. Basic MOS Amplifiers & Small-Signal Analysis 42
(6-3) 저항성 부하를 갖는 NMOS 차동증폭기(2)
Half-circuit 개념을 이용한 Small signal analysis
VDD RL
Vo1
Vin1 M1 M2
Vo2
Vin2
VSS
ID1
ID2 M3
DC Bias
Differential mode
Half circuit RL RL G1 D1 +
vgs1
gm1vgs1
ro1 - M1 S1
Common
mode
Half circuit RL RL G1 D1 + M1
vgs1
gm1vgs1
ro1 -
½ M3 S1
2ro3

62. (6-3) 저항성 부하를 갖는 NMOS 차동증폭기(3)
4. Basic MOS Amplifiers & Small-Signal Analysis 43
(6-3) 저항성 부하를 갖는 NMOS 차동증폭기(3)
Active input common mode range é I ù V + ( V - V ) V
min V - R SS + V ê ú GS 1 GS 3 TH 3 in , CM ë DD D 2 TH û
VDD RD
Vout1
Vin, CM M1 M2 Vb M3
Vout2
VTH V1 V2
Vin,CM
Small-signal differential mode voltage gain

63. Differential mode input  두배 Common mode input  상쇄되어 없어짐
4. Basic MOS Amplifiers & Small-Signal Analysis 44
(6-4) 능동(Active) 부하를 갖는 NMOS 차동증폭기(1)
Differential to single ended amplifier
VDD
VDD
Current mirror M4 M5 M4 M5 Vo Vo M1 M2 M1 M2
Vi1
Vi2
Vi1
Vi2
DC bias M3
DC bias M3
VSS
VSS
Differential mode input  두배
Common mode input  상쇄되어 없어짐

64. (6-4) 능동(Active) 부하를 갖는 NMOS 차동증폭기(2)
4. Basic MOS Amplifiers & Small-Signal Analysis 45
(6-4) 능동(Active) 부하를 갖는 NMOS 차동증폭기(2)
출력저항 ( RO ) R1
ro2
ro4
ro5
ro3
rS4
rS2 v1
rS1 v4
ro1
rS5 R4
R’1 R2
CG입력저항
Current mirror
CG출력저항

65. (6-4) 능동(Active) 부하를 갖는 NMOS 차동증폭기(3)
4. Basic MOS Amplifiers & Small-Signal Analysis 46
(6-4) 능동(Active) 부하를 갖는 NMOS 차동증폭기(3)
차동모드 트랜스컨덕턴스 (Gmd ) R1
ro2
ro4
ro5
ro3
rS4
rS2 v1
rS1 v4
ro1
rS5 R4
R’1 R2

66. (6-4) 능동(Active) 부하를 갖는 NMOS 차동증폭기(4)
4. Basic MOS Amplifiers & Small-Signal Analysis 47
(6-4) 능동(Active) 부하를 갖는 NMOS 차동증폭기(4)
공통모드 트랜스컨덕턴스 (Gmc) R1
ro2
ro4
ro5
ro3
rS4
rS2 v1
rS1 v4
ro1
rS5 R4
R’1 R2
*유도과정 : 참고(박홍준 ; CMOS아날로그 집적회로 p337)

67. (6-4) 능동(Active) 부하를 갖는 NMOS 차동증폭기(4)
4. Basic MOS Amplifiers & Small-Signal Analysis 48
(6-4) 능동(Active) 부하를 갖는 NMOS 차동증폭기(4)
공통모드 이득 제거율 (Common mode rejection ratio : CMRR)
Avc - +
Vin_com
Vout
VSS
VDD
공통모드 신호 증폭
Avd
CMRR =
Avc

68. NMOS 차동입력단 CMR max CMR min
4. Basic MOS Amplifiers & Small-Signal Analysis 49
(6-4) 능동(Active) 부하를 갖는 NMOS 차동증폭기(5)
Active input common mode voltage range (CMR)
CMR : 최대의 이득을 얻기 위해 모든 트랜지스터 들이
saturation영역에서 동작하기 위한 입력 전압범위
VDD
NMOS 차동입력단
CMR max M4 M5 Vo M1 M2
Vi1
Vi2
CMR min
DC bias M3
VSS

69. PMOS 차동입력단 CMR max CMR min NMOS 차동입력단 PMOS 차동입력단 VSS VDD
4. Basic MOS Amplifiers & Small-Signal Analysis 50
(6-4) 능동(Active) 부하를 갖는 NMOS 차동증폭기(6)
Active input common mode voltage range (CMR)
PMOS 차동입력단
Vin - M1 M2
VDD M5 M3
VSS M4
Vin +
CMR max
CMR min
NMOS 차동입력단
PMOS 차동입력단
VSS
VDD

70. (6-5) CS Push-Pull Amplifier
4. Basic MOS Amplifiers & Small-Signal Analysis 51
(6-5) CS Push-Pull Amplifier
VDD
vout
vin
VSS M1 M2
VDD
vout
vin
VSS M1 M2
VB2 + -
VB1 S2 +
vsg2
ro2
gm2vsg2
vin G2 - D2
vout
vin G1 + D1
ro1
vgs1
gm1vgs1 - S1
M1 과 M2는 각각 Amplifier 이면서 Load 로 동작됨
M1 과 M2의 Gate에 Bias Circuit가 요구됨
By vout - node
gm2vsg2 = gm1vgs1+ vout /ro1 + vout /ro2
gm2 (0-vin) = gm1 (vin-0) + vout /ro1 + vout /ro2
vout
A v =
(gm1+ gm2) (ro1 II ro2) = -
vin

71. 5. Current Sources & Mirrors52
5. Current Sources & Mirrors
(1) Passive & Active Loads
Passive Load
Ideal Current Source
Active Load
VDD
VDD
vout
vin
VSS
Ideal
Current
Source IB
VDD
vout
vin
VSS
Active
Load
VGG
Passive
Load 구 조 RL
vout
vin
VSS
Loading RL
rop
Biasing
(VDD - VOUTQ)/ RL IB
IMP

72. Operating Resistance Rout
5. Current Sources & Mirrors 53
(2) Ideal & Active Current Sources
Equivalent Circuit
I-V Curve
Characteristics
Iout
Output current (Iout)
should be independendent of an output voltage (Vout)
Iout +
Ideal
Current
Source
Vout -
Vout
Iout
Operating Range
Iout +
Large Signal Analysis
Active
Current
Source
Vout
dIout
Operating Resistance Rout
Slope =
= Rout-1 -
dVout
Small Signal Analysis
Vout
Operating range

73. VDS(sat) =VGS-VTH =VB-VTH
5. Current Sources & Mirrors 54
(3) Simple NMOS Current Sources
Equivalent Circuit
I-V Curve
Output Resistance
Iout
Iout = IDS + VB
Vout
dIout -
Slope =
= rout-1
dVout vx 1
Rout =
= ro = ix go
Vout= VDS ix
VDS(sat) =VGS-VTH =VB-VTH + +
vgs ro vx
gmvgs -
IDS(sat) = b/2(VGS- VTHn)2 = b/2 D2 -
2IDS(sat) b
Vout
D =

74. (4) Cascode Current Sources
5. Current Sources & Mirrors 55
(4) Cascode Current Sources
Equivalent Circuit
Characteristics
Vout + -
Iout
VB1
VB2 M2 M1 vx ix
Output Resistance vx
Rout =
= ro1 + ro2 + (gm2ro2)ro1 ix
(gm2ro2)ro1
Operating Range +
Down to 2D
vgs2
ro2 ix
gm2vgs2
More Stacking :
Problem for Low-Supply Applications - + vx + -
vgs1
ro1
gm1vgs1 -

75. (5) Advanced Cascode Current Sources
5. Current Sources & Mirrors 56
(5) Advanced Cascode Current Sources
Equivalent Circuit
Characteristics
Output Resistance A ix
VB2 + M2 - + vx
By vx-node M1 -
VB1 ix
gm2vgs2+ gmb2vbs2 + go2 (vx-vy) =
gm2[A(0-vy)-vy]+ go2(vx-vy) =
(0-vy)A + A
By vy-node - +
vgs2
ro2 ix
gm1vgs1+ go1 vy ix = =
go1 vy
gm2vgs2 - + vx vy + - vx
Rout =
= ro1 + ro2 + (A+1)(gm2ro2)ro1
vgs1
ro1 ix
gm1vgs1 -
A(gm2ro2)ro1

76. (6) Basic Current Mirror
5. Current Sources & Mirrors 57
(6) Basic Current Mirror M2
Iout
VSS
Iin M1 D
M1 : Current Input
M2 : Current Output
M1와 M2가 Ideal Matching 일때, I1= I2
Operating Range : Down to D
Output Resistance : Rout= ro2
Mismatch Problem
( )2( VGS-VTH2)2 ( 1+ lVDS2) W L 1 2
m Cox
Iout =
Iin
( )1( VGS-VTH1)2 ( 1+ lVDS1) W L 1 2
m Cox
transistor size W/L
threshold voltage
VDS

77. (7) Wilson Current Mirror (1)
5. Current Sources & Mirrors 58
(7) Wilson Current Mirror (1) M1
Iout
Iin M3 M2 V1 V2
VDD
Rin
Rout
Vout + -
M1, M2 는 소신호 피이드백 경로가 됨
V2가 증가하여 전류 Iout이 증가하면
V1증가하므로 M1의 증폭으로 V2가 크게 감소함
결국 VGS3가 감소 하게 되어 Iout이 감소하게 됨.
이와 같은 과정은 역으로도 진행되어
Iout이 일정하게 유지됨 --> 소신호 출력저항이 큰값
출력저항 (Rout) + -

78. (7) Wilson Current Mirror (2)
5. Current Sources & Mirrors 59
(7) Wilson Current Mirror (2) M2
Iout
VSS
Iin M1
VTH + D M3 D
Operating Range : Down to VTH + 2D
VDS Mismatch
VDS1 = VGS3 + VGS2 = VGS3 + VDS2 > VDS2 M2
Iout
VSS
Iin M1
VTH + D M4 D M3
Improved Version
Operating Range : Down to VTH + 2D
Same Performance but
VDS1 = VGS3 + VGS2 - VGS4 = VGS3 + VDS2 - VGS4
VDS2

79. (8) Cascode Current Mirror(1)
5. Current Sources & Mirrors 60
(8) Cascode Current Mirror(1)
Iin
Iout
Output Resistance : Rout = (gm4ro4)ro2
VTH + D M3 M4
Operating Range : Down to VTH + 2D D
VDS Mismatch Avoided
VDS1 = VGS4 - VGS2 + VDS2
VTH + D M1 M2
VTH + D
VDS2
VSS
Iin
Iout
Operating Range Improved Version : 2D
VTH + D
VTH + 2D
Output Resistance : Rout = (gmro)ro D
VTH + D D
VSS

80. (8) Cascode Current Mirror(2)
5. Current Sources & Mirrors 61
(8) Cascode Current Mirror(2)
Small signal analysis M1 M2 M3 M4 M1 M2 M2
 M1 : saturation
 M2 : saturation

81. (8) Cascode Current Mirror(3)
5. Current Sources & Mirrors 62
(8) Cascode Current Mirror(3) M1 M2 M3 M1 M2 M3 M4 M5 M6
 M1 : saturation
 M2 : saturation
 M3 : saturation

82. (8) Cascode Current Mirror(4)
5. Current Sources & Mirrors 63
(8) Cascode Current Mirror(4)
Ma1
Mb1
Ma0
Mb0
Ma2
Mb2
Ma3
Mb3
Man
Mbn
VDD