1. 1 DEPFET Readout Electronics Ivan Peric, Jochen Kinzel, Christian Kreidl, Peter Fischer University of Heidelberg

2. 2 Introduction

3. 3 DEPFET readout and control-ASICS DCD#0 – DCD#5 Switcher#0 Switcher#4 ACTIVE AREA Sensor – active area Sensor balcony Chip Switcher – row control chip with high voltage line drivers 0.35 μm technology DCD – DEPFET current receiver and digitizer chip 0.18 μm technology DHP – Digital data handling and readout control chip 0.09 μm technology 960X512 (160 channels each) (32 channels each) Bump bonding Fan-out Switcher DCD DHP

4. 4 Switcher with LV transistors – Switcher 3 Switcher 3 Radiation tolerant layout in 0.35 μm technology 128 channels + Very fast - Operation up to 11.5 V Novel design: Uses stacked LV transistors, HV twin-wells and capacitors as level- shifters + No DC power consumption - SEU causes shorts HV channel with 3+3 Switch transistors and 4 AC coupling stages (180x180µm, M4 not shown) interdigitated AC coupling caps Ivan Peric, Mannheim 80µm opening

5. 5 Switcher 3 – output driver Use an SRAM cell flipped by a transient voltage No dc power consumption! 9V out ‘SRAM’ 3V ‘SRAM’ 6V ‘SRAM’ 0V 3V 6V Reset ~200 fF

6. 6 Switcher 4 Switcher 3 Uses radiation tolerant high voltage transistors in HV 0.35 μm technology 64 channels - Not as fast + Possible operation up to 50 V (30V tested) - moderate DC power consumption (32 X 30uA X 12V = 11.52mW) Enclosed design of NMOS HV transistors

7. 7 Switcher 4 chip – high voltage transistors Hi voltage 20V0V 17-20V0-3V 0-20V Thin oxide Thick oxide n- p- n- Vertical NMOS PMOS

8. 8 D S D S Thick oxidLeakage current Standard NMOS Annular gate NMOS G G Annular gate vertical NMOS S B G D Difefrent types of radiation-soft and -hard NMOS transistors

9. 9 logic out 20V 17V 3V 0V in Switcher 4 chip output driver

10. 10 DCD3 chip - Technology 0.18 μm - 72 Channels - 2 ADCs and regulated cascode/channel - 6 channels multiplexed to one digital LVDS output - ADC sampling period 160 ns (8 bits) - Channel sampling period 80 ns - LVDS output: 600 M bits/s - Chip: 7.2 G bits/s (12 outputs) - Radiation tolerant design - ~ 1mW/ADC (optimal powering) - ~ 1mW/Cascode

11. 11 DCD 3 measurements ADC characteristicNoise

12. 12 DCD3 ADC Reg. cascode Double sampling DEPFET W NC R R R R L L R R W R R L L W R 1 2 3 4 5 6 7 1 2 3 4 5 6 7 77 7 77 66 55 5 4 3 5 4 3 66 77 3 Gate On

13. 13 SO A1 A2 B1 B2 S S S S S2S-R S S DCD conversion principle

14. 14 wrrrnc lt ncccwr nc lt rdlt rd wrncrr rdlt rd ncwrcc rrnc rd lt ncccwr rd lt rdlt rd wrncrr rdlt rd ncwrcc SS 2(S-h 0 R+l 0 R) 2(2(2(2(S - h 0 R + l 0 R) - h 1 R + l 1 R) – h 2 R + l 2 R) – h 3 R + l 3 R) = Res wrrrnc lt S‘ h0h0 l0l0 h1h1 l1l1 h2h2 l2l2 h3h3 l3l3 sample state 1sample state 2state3state4 state1state2state3state4sample state 1 2(2(S-h 0 R+l 0 R)-h 1 R+l 1 R) 2(2(2(S-h 0 R+l 0 R)-h 1 R+l 1 R)–h 2 R+l 2 R) memory cell comparator rd – read wr – write nc – not connected r – reset c – compare lt - latched States: 1.2. 3.4. 1.2. 3.4. ck2ck1ck3ck4 ck6ck5ck7ck8ck9 Res DCD conversion principle

15. 15 A2A1B2B1 Gate Current Clear Wr S 80ns 25ns Wr O 25ns S S Timing

16. 16 Pad Logic Current receiver Data compression Power line 180um 110um Channel geometry 1000uA

17. 17 DCD Improvements

18. 18 Improvements Dynamic range (radiation damage) Speed (background) Pickup noise immunity (environmental noise) Noise (presently 100e) Geometry (compatibility with solder bump technologies) Power (cooling, voltage drops) Dynamic Range: DKS with large input cell, modified ADC algorithm, scaled pipeline ADC Sample speed: Single sampling, clear without return to baseline ADC speed: pipeline ADC Noise: DKS with single sampling cell, single sampling Pickup noise immunity: DKS, differential readout Power: Simplified comparator, resistance instead SF

19. 19 Improvements – large Input cell/modified algorithm SO A1 A2 B1 B2 S S S S S S S S2S-R S S S/2 S-R S/2 ADC with large input cell Modified algorithm Original algorithm

20. 20 wrrrnc lt ncccwr nc lt rdlt rd wrncrr rdlt rd ncwrcc rrnc rd lt ncccwr rd lt rdlt rd wrncrr rdlt rd ncwrcc SS 2(S-h 0 R+l 0 R) 2(2(2(2(S - h 0 R + l 0 R) - h 1 R + l 1 R) – h 2 R + l 2 R) – h 3 R + l 3 R) = Res wrrrnc lt S‘ h0h0 l0l0 h1h1 l1l1 h2h2 l2l2 h3h3 l3l3 sample state 1sample state 2state3state4 state1state2state3state4sample state 1 2(2(S-h 0 R+l 0 R)-h 1 R+l 1 R) 2(2(2(S-h 0 R+l 0 R)-h 1 R+l 1 R)–h 2 R+l 2 R) memory cell comparator rd – read wr – write nc – not connected r – reset c – compare lt - latched States: 1.2. 3.4. 1.2. 3.4. ck2ck1ck3ck4 ck6ck5ck7ck8ck9 Res Original algorithm

21. 21 wrrr nc lt nccc lt rdlt rd wrncrr rdlt rd ncwrcc rrnc rd lt ncccwr rd lt rdlt rd wrncrr rdlt rd ncwrcc S 2(S/2-h 0 R+l 0 R) 2(2(2(2(S/2 - h 0 R + l 0 R) - h 1 R + l 1 R) – h 2 R + l 2 R) – h 3 R + l 3 R) = Res wrrrnc lt S‘ h0h0 l0l0 h1h1 l1l1 h2h2 l2l2 h3h3 l3l3 sample state 1sample state 2state3state4 state1state2state3state4sample state 1 2(2(S/2-h 0 R+l 0 R)-h 1 R+l 1 R) 2(2(2(S/2-h 0 R+l 0 R)-h 1 R+l 1 R)–h 2 R+l 2 R) memory cell comparator rd – read wr – write nc – not connected r – reset c – compare lt - latched States: 1.2. 3.4. 1.2. 3.4. ck2ck1ck3ck4 ck6ck5ck7ck8ck9 Res Modified algorithm

22. 22 s Gate Current after cascode Clear Sample 80ns 25ns ss 55ns so DKS Single sampling DKS vs. single sampling

23. 23 ss Gate Current after cascode Clear Sample 75ns 25ns ss 50ns so DKS Single sampling Fast clear

24. 24 AND ld Reset D Fast clear – switcher modification

25. 25 A2A1B2B1 SO A1 A2 B1 B2 Gate Current Clear Wr S 80ns 25ns Wr O 25ns Double-cell DKS Noise ~ 100e LSB ~ 160e

26. 26 SB1 B2 A2A1B2B1 Gate Current Clear Wr S 80ns 25ns A1 A2 Single-cell DKS Noise ~ 100e/1.41 LSB ~ 160e

27. 27 SB1 B2 A12B12 Gate Current Clear Wr S 80ns 25ns A1 A2 Single-cell DKS Noise ~ 100e/1.41 LSB ~ 320e

28. 28 SB1 B2 A12B12 Gate Current Clear Wr S 80ns 25ns SS SA1 A2 Single-cell DKS Noise ~ 100eX1.41 LSB ~ 320e

29. 29 ADC Cell Vbias 24 μ A R Sub Add WrB* WrBRdB Rd Wr RefIn AmpLow Gate 24 μ A 6X2 μ A 12 μ A Logic C1C2 Hi Lo Rd To Comp In? Or use Th instead

30. 30 ADC Cell – low-power scheme Vbias 24 μ A R Sub Add WrB* WrBRdB Rd Wr RefIn AmpLow Gate 24 μ A 6X2 μ A 12 μ A Logic C1C2 Hi Lo Rd To Comp In? Or use Th instead

31. 31 Comparator Vbias 24 μ A Th ResB Gate AmpLow ResBLB RefIn L 24 μ A 6X2 μ A 12 μ A Comp In Or th

32. 32 Comparator – low-power scheme Vbias 24 μ A Th ResB Gate AmpLow ResBLB RefIn L 24 μ A 6X2 μ A 12 μ A Comp In Or th

33. 33 Cascode 1 mA 0.3 mA 1 V 1.8 V Vbias 40 μ A

34. 34 Novel readout concept - pixel difference readout

35. 35 abcdabcd -- 4pixels/80ns 4pixels/40ns ab a > th ? (a - hit : a - not hit) a-b > 0 ? (a - hit : b - hit) Pixel difference readout

36. 36 Pixel difference readout vs standard readout + Differential readout – immune against pickup – operation without DKS possible, no need for common mode correction + 2X less ADC channel needed + doubled conversion speed by the same number of ADC cores + if used without DKS sampling speed can be doubled + compatible with standard readout - lost hits when both coupled pixels generate the same signal - by one reduced number of bits (7 vs 8 bits) - in the case of used DKS, larger noise by 1.41

37. 37 4-7 0 1 2 3 4 5 6 7 0-3 16 17 18 19 16-19 24-27 20-23 20 21 22 23 24 27 Connection scheme

38. 38 0 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23 24 27 0 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23 24 27 Not detected Detected 0 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23 24 27 0 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23 24 27 Detected Lost hits

39. 39 abcd -- 4pixels/40ns + + - a+b-(c+d)? <0>0 =0a or b c or d ac, ad, bc, bd or none c-d? cd a-b? ab c-d? ac, bcad, bd none a-b? adbd a-b? acbc ab cd Scheme with error correction

40. 40 Pixel difference readout and efficiency A err

41. 41 Pixel difference readout and efficiency A err

42. 42 A err Pixel difference readout and efficiency

43. 43 Pixel difference readout and efficiency

44. 44 DCD channel geometry

45. 45 Pad Logic Current receiver Data compression Power line 180um 110um Channel geometry

46. 46 185um 110um Channel geometry

47. 47 160um 110um Channel geometry

48. 48 1:11:1.5 10X16 8X20 150 um 190 um

49. 49 Digital Part 10X16 geometry

50. 50 8X20 geometry

51. 51 8X20 geometry with in pixel data compression (for test chip)

52. 52 8X20 geometry with in pixel data compression and 110um pitch (for test chip) 2 miniasics

53. 53 16X8 wire bond DCD geometry (1) 2 miniasics

54. 54 16X8 wire bond DCD geometry (2)

55. 55 8X20 + nice and easy fan out on sensor + additioal space for improved ADC if necessary + same cell geometry can be used for both bump- and wire bond DCD + possibility to implement data compression in the cell like in DCD2 8X20 with data compression in the cell + desin already exists – can be used as alternative for test chips + smaller chips possible (2 miniasic) – good for testing eg with bump bond adapter 10X16 + less cells in a collumn ??

56. 56 Some ideas on test system – to be done with Bonn

57. 57 Dig1 Dig2 400MHzCk, RowRes, ClearSync 400MHzCk, RowRes, FrameRes, FrameID, Triger SIn, RowCk, Clear, Gate ROCk DO100MHzCk, Trigger, Reset ROCk, DO DCD FanOut DEPFET SWITCHER Possible test system architecture RowRes, ClearSync, 400MHzCk 100MHzCk

58. 58 SB1 B2 A12B12 Gate Current Clear Wr S 80ns 25ns SS SA1 A2 Single-cell DKS Generated by DIG2

59. 59 Pad Logic Current receiver Data compression Power line 180um 110um Power 84uA 72uA 1000uA

60. 60 ADC Cell Vbias 24 μ A R Sub Add WrB* WrBRdB Rd Wr RefIn AmpLow Gate 24 μ A 6X2 μ A 12 μ A Logic C1C2 Hi Lo Rd To Comp In? Or use Th instead

61. 61 ADC Cell Vbias 24 μ A R Sub Add WrB* WrBRdB Rd Wr RefIn AmpLow Gate 24 μ A 6X2 μ A 12 μ A Logic C1C2 Hi Lo Rd To Comp In? Or use Th instead

62. 62 Comparator Vbias 24 μ A Th ResB Gate AmpLow ResBLB RefIn L 24 μ A 6X2 μ A 12 μ A Comp In Or th

63. 63 Comparator Vbias 24 μ A Th ResB Gate AmpLow ResBLB RefIn L 24 μ A 6X2 μ A 12 μ A Comp In Or th

64. 64 Cascode 1 mA 0.3 mA 1 V 1.8 V Vbias 40 μ A

65. 65 Powering of the DCD

66. 66 Pad Logic Current receiver Data compression Power line 180um 110um Power 84uA(60uA) 72uA(24uA) 1000uA 2XADC: 72uAX8+84uAX12=1584uA Chip: 2.5mAX160=400mA Pixel: 1.5mA + 1mA

67. 67 Pad Logic Current receiver Data compression Power line 180um 110um Power 84uA(60uA) 72uA(24uA) 1000uA 2XADC: 24uAX8+84uAX12=1200uA Chip: 2.2mAX160=352mA Pixel: 1.2mA + 1mA

68. 68 Pad Logic Current receiver Data compression Power line 180um 110um Power 84uA(60uA) 72uA(24uA) 1000uA 2XADC: 24uAX8+60uAX12=912uA Chip: 2.2mAX160=320mA LVDS=40X1mA=40mA? Pixel: 1mA + 1mA

69. 69 Regulators 1.8V 3.3V V+Ref+ Ref- vdda 1.8V 1.2V gnda 0+Error 0.6+Error 1.2V 0.6+Error 1.8+Error 1.8V 3.3VPMOS DCD1DCD6 vdda Gnda Ref- VPlus Ref+ x 0.4V 2.4V Error 0.2V

70. 70 Power lines 3.5mm 2mm V+ gnda 320mAX6 1AX0.21Ohm=210mV 35mOhmX6mm/1mm=0.21Ohm 12mm VSS

71. 71 Pad Logic Current receiver Data compression Power line 180um 110um Power 84uA(60uA) 72uA(24uA) 1000uA Power =160 X (2.7mW(ADC)+1.8mW(casc))=720mW (1.8V) Power =160 X (2.0mW(ADC)+1mW(casc))=480mW (optimized) Power =160 X (3.6mW(ADC)+2.4mW(casc))=960mW (2.4V) Power = 160 X (2.7mW(ADC)+1mW(casc))=592mW (VSS, 1.8V) Power =160 X (3.6mW(ADC)+1.4mW(casc))=800mW (VSS, 2.4V)640mW

72. 72 Power lines 3.5mm 2mm V+ gnda 12mm RefIn VSS DHP

73. 73 Possible test system architecture – DIG1 015 CAM 063 0 Triggered Hits A,C,R,ID,TR,TID,R wr Col Row Trigger Frame ID 1 DCD 400MHz ROCk Data 400MHzCk, RowRes, FrameRes

74. 74 After 8X20ns DCD ADCs ShiftIn ParIn Register One LVDS link Possible test system architecture

75. 75 Row (1-noofrows) Col (1-64) 160ns CkT = 160ns/64 SRAM Delay 16X 16X4=64Bytes CAM Delay Wr FrameRes RowRes FrameID TriggerFrame F1 R1RiRn F2 R1RiRn TriggerRow TriggerDelay ROFIFO (…) 2X this on the chip FrameID Row Trigger TriggerDelay Rd ROCk Data 16 LVDS links Possible test system architecture

76. 76 Dig1Dig2 400MHzCk, RowRes, FrameRes, FrameID, Triger, RoCK SIn, RowCk, Clear, Gate DO 100MHzCk, Trigger, Reset ROCk, DO DEPFET SWITCHER Dig1 400MHzCk, RowRes, ClearSync Dig1 RowRes, ClearSync, 400MHzCk 100MHzCk Possible large test system architecture

77. 77 Dig1Dig2 400MHzCk, RowRes, FrameRes, FrameID, Triger, RoCK SIn, RowCk, Clear, Gate DO 100MHzCk, Trigger, Reset ROCk, DO DEPFET SWITCHER Dig1 RowRes, ClearSync, 400MHzCk 100MHzCk Possible large test system architecture