1. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 DEVELOPPEMENTS DE SYSTEMES D’ACQUISITION ANALOGIQUE MULTIGIGAHERTZ D.Breton & J.Maalmi (LAL Orsay), E.Delagnes (CEA/IRFU)

2. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Introduction La technologie a évolué d’une façon impressionnante ces dernières années. Ceci est vrai aussi bien pour les circuits ou les cartes que pour les outils logiciels disponibles pour leur réalisation. Parfois nous trouvons “sur l’étagère” les circuits ou cartes dont nous avons besoin. Parfois il faut les réaliser nous-mêmes, et dans certains cas nous pouvons nous retrouver à la pointe du domaine au niveau mondial. Je commencerai ma présentation par une introduction générale à la problématique de la conversion analogique/digitale à haute fréquence puis je vous montrerai les solutions originales que nous avons développées, en particulier ces dernières années grâce à P2I. Je vous présenterai en français des slides composés en anglais : apologies for that …

3. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 La chaîne d’acquisition de données A quoi ressemble une chaîne d’acquisition de données dans notre domaine ? Captors Trigger System Trigger primitives Trigger, CLK, CMDs Control & Test Bench FPGA: - Evt Buffer - Post-Processing: digital filtering - … PC- Farm Ethernet PCI/PCIx Acquisition Board FE Chip ADC amplitude time FPGA: - Evt Buffer - PreProcessing: FFT, CFD… - … USB, Field Bus… TDC Processor Ctrl System Optical Links Gbits/s Trigger Front End Board

4. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 New trends in data acquisition are to digitize the signal as soon as possible in the chain and to perform a digital treatment of information Waveform indeed contains all information (if properly digitized) Depending on the information requested (amplitude, charge, time, FFT, …), different types of algorithms will be used Goal is to find the simplest effective algorithms which could be integrated within companion FPGAs Waveforms can be used for designing high performance TDCs Signal to noise ratio is always an issue, even for a for TDC In some cases, it is mandatory to use ADCs When the trigger is performed on digitized data (high-end oscilloscope) When a constant data stream is necessary (even if the latter will end up in the companion FPGA) => real time FFT for instance (radar) But whenever a short time window and a reasonable hit rate are present, analog memories are worth being considered State of the art: digitization

5. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 About fast ADCs … An ADC converts an instantaneous voltage into digital value. It is characterized by: –Its signal bandwidth –Its sampling frequency –Its number of bits (converted / effective) –Collateral dammages : Their package, consumed power, output data rate ! The most powerful products on the market: 8bits => 3GS/s, 1,9 W => 24Gbits/s, 10 bits => 3GS/s, 3,6 W => 30Gbits/s 12 bits => 3,6GS/s, 4,1 W => 43,2Gbits/s 14 bits => 400MS/s, 2,5 W => 5,6Gbits/s => appearance of integrated circular buffers (limited by technology) –Big companies are experts => our only potential benefit to design ADCs is to integrate them within more complex circuits BGA 292 pins 24x1,8Gbits/s Need of a VERY high-end FPGA  power, cost, board design complexity, …  and what about radiation if any ? 1.8 GHz !

6. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 About fast ADC boards … Designing a board with an ADC producing tens of Gbits/s is a huge effort –High-end FPGAs have to be used –If one wants to record some time depth, banks of DDR3 RAMs have to be used A few companies started the exercise These boards are expensive (5 to 40 k$) and house very few channels (the most often 2 channels sharing the ADC and thus the GS/s) This is perfect for very high precision and very little scale, and for systems where dead-time before digitization is critical This is more a problem for high scale and low power …

7. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 About high speed TDCs … Existing electronics for time measurement is mostly based on Time to Digital Converters (TDC). A TDC converts the arrival time of a binary signal into digital value. It is characterized by : –Its time step and its main clock frequency –Its effective resolution (which can be very different from time step) –Its dead-time and its mean maximum hit rate –Its number of channels Very few high-end products on the market, mostly dedicated to LHC –HPTDC from CERN => 25ps & 40MHz –TDC-GPX from ACAM => 8 channels, 80ps & 40MHz –There is an important demand for time of flight measurement in the medical community, and now for ps precision in high energy physics But analog signal has to be translated into binary by a discriminator before being sent to the TDC itself

8. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Why Analog Memories ? Analog memories actually look like perfect candidates for high precision measurements at high scale: –Like ADCs they catch the signal waveform (this can also be very useful for debug) –TDC is built-in (position in the memory gives the time) –Only the useful information is digitized (vs ADCs) => low power –Any type of digital processing can be used –Main difficulty is less sampling frequency than signal bandwidth Their drawbacks: –The limited recording depth –The readout dead-time But: –Only a few samples/hit can be read => this may limit the dead time –Simultaneous write/read operation is feasible, which may further reduces the dead time if necessary

9. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 History of the Orsay/Saclay SCA developments The story began in 1992 with the design of the first prototype of the Switched Capacitor Array (SCA) for the ATLAS LARG calorimeter. After 10 years of development, the main final characteristics of this rad-hard circuit were: 12 pseudo-differential channels 40 MHz sampling 13.6-bit dynamic range with simultaneous write/read Rad tolerance: few Mrads 80000 chips produced in 2002, now on duty on the LHC. Since 2002, 3 new generations of fast samplers have been designed (ARS, MATACQ, SAM): total of more than 30000 chips in use. Our design philosophy: 1. Maximize dynamic range and minimize signal distorsion. 2. Minimize need for calibrations and off-chip data corrections. 3. Minimize costs (both for development & production): Use of inexpensive pure CMOS technologies (0.8µm then 0.35µm); Use of packaged chips (cheap QFP).

10. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Basic principles of circular analog memory A write pulse is running along a folded delay line (DLL). Sampling stops upon trigger. Readout can target an area of interest: – Starting from Trigger cell (marked during signal recording) - programmable offset (linked to latency). Total readout can however be performed. Dead time due to readout has to remain as small as possible (<100ns / sample).

11. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Our improved DLL scheme Here, time propagation is servo controlled => individual delays are much more precise and should not vary with time. With a 200 MHz clock and 16 delay cells, we sample at 3.2GS/s

12. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 The Sampling Matrix Structure: main features ADC On board 12 bits 20 MHz Patented in 2001

13. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Our former development: the MATACQ boards The MATACQ boards (2002-2008) house 4 channels sampling analog data along 2560 cells up to 2 GSample/s with an analog bandwidth of 300 MHz, and digitizing it with a 14-bit dynamic range. It is based on the custom-designed MATACQ chip. The latter’s innovative design permits reaching these performances with power consumption < 1W. The boards are triggerable either by internal or external signals and several boards are easily synchronizable. The board integrates USB, GPIB and VME interfaces that permit a maximum readout speed of 500 events/s with the whole memory depth of the 4 channels read.

14. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 The SAM (Swift Analog Memory) chip NIM A, Volume 567, Issue 1, p. 21-26, 2006 This chip was first designed for HESS2 experiment: a big Athmospheric Cerenkov Telescope located in the Namibia desert. 2 differential channels 256 cells per channel BW > 250 MHz Sampling Freq: 700MHz-2.5GHz High Readout Speed >16 MHz Smart Read pointer (integrate a 1/Fs step TDC) Few external signals Many modes configurable by a serial link. Auto-configuration @ power on Low cost for medium size prod=> AMS 0.35 µm 6000 ASICs delivered in Q2 2007, yield of 95%.

15. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Characterization is always fruitful … In parallel to the funding request to P2I, we developed the first board based on SAM which should not present obvious performance limitations for the circuit. –And there we realized that the chip hadn’t been pushed towards its limits –We then started measuring its actual ultimate performances –At the same time, we were contacted by the members of the international ps collaboration  thanks to P2I, we could design a new version of the board (V2), targeting the study of the ps time precision –We then spent 1 year trying to understand every little detail of its behavior V1 V2

16. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 1.5 GHz BW amplifier. Trigger discriminators The USB_WaveCatcher prototype board (V2) SAM Chip Dual 12-bit ADC µ USB Reference clock: 200MHz => 3.2GS/s 2 analog inputs. DC Coupled. Trigger input Pulsers for reflectometry applications Board has to be USB powered => power consumption < 2.5W Trigger output Cyclone FPGA +5V Jack plug The module

17. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Board Special Features  Possibility to add an individual DC offset on each signal  Individual trigger discriminator on each channel  External and internal trigger + numerous modes of triggering on coïncidence (11 possibilities including two pulses on the same channel => useful for afterpulse studies  Real time trigger counting independent of acquisition rate  Embedded charge mode (integration starts on threshold or at a fixed location) => high rates (~ 5 to 10 kEvents/s)  Embedded pulse generators for reflectometry applications

18. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 CVI acquisition software with GUI This oscilloscope-like software was developed by the team.

19. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Window for time measurements

20. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Focusing points for the study The board is a waveform digitizer. The analog memory records analog samples which will be digitized by an ADC after selection by a trigger system (which can be a simple discriminator). The quality of the signal recorded in the memory mainly depends on: –The dynamic range and signal bandwidth –The level of electronics noise –The signal non-linearity –The time precision of the sampling instants. When dealing with precise time measurement (ps level), all sources of jitter have to be carefully studied –These sources can be purely temporal or the consequence of other types of noise

21. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Jitter induced by electronics noise Conclusions:  The higher the SNR, the better for the measurement  A higher bandwidth favours a higher precision (goes with its square root).  But: for a given signal, it is necessary to adapt the bandwidth of the measurement system to that of the signal in order to keep the noise-correlated jitter as low as possible  Designs become tricky for ultra fast signals with a bandwidth > 1GHz … Time Zoom Noise Jitter Time Jitter [ps] ~ Noise[mV] / Signal Slope [mV/ps] ~ t r / SNR Ex: the slope of a 100mV - 500MHz sinewave gets a jitter of ~2ps rms from a noise of 0.6mV rms Simplified approach slope = 2ЛAf 3db tr ~ 1/(3 f 3db )

22. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Dispersion of single delays => time DNL Cumulative effect => time INL. Gets worse with delay line length. Systematic & fixed effect => non equidistant samples (bad for FFT) => Time Base Distortion We can measure it => we can store it on-board => it can be corrected automatically by software (transparent for user) Effects of the Fixed Pattern Jitter Real signal Fake signal After interpolation Δt[cell] In a Matrix system, DNL is mainly due to signal splitting into lines => modulo 16 pattern if 16 lines Remark: same type of problem occurs with interleaved ADCs (oscilloscopes)

23. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Time calibration  Method: search of zero-crossing segments of a sine wave => length[position]  Length[position] is proportional to time step duration assuming that: sine wave is a straight line (bias ~ 2ps rms).  Sine wave characteristics: 70MHz -1.4Vpp  Higher frequency => may be bothered by slew rate  Lower frequency => lower slope => more jitter because of noise

24. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Jitter calibration method DLL jitter Clock jitter 1.95ps rms Random jitter 7.5ps rms DNL  Histogram of Length[position]:  Mean_Length[position]: Fixed Pattern => DNL after integration => INL  Sigma_Length[position]: Random effect => Random Jitter

25. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Jitter calibration 16.9ps rms 1.5ps rms Raw INL Re-Calibration after correction The INL correction is stable over a long period of time (months …) => INL values are constants and stored in the on-board EEPROM. Integration 7.5ps rms DNL => correction with second order polynomial interpolation to recover equidistant samples

26. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 WaveCatcher characterization setup USB Wave Catcher Open cable USB Wave Catcher Two pulses on the same channel Two pulses on different channels => with this setup, we can measure precisely the time difference between the pulses independently of the timing characteristics of the generator!  For the least jitter at short distance … USB Wave Catcher  For other distances : * Two pulses generated with a programmable distance (high-end Agilent generator) HP81110/12/12

27. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 The easiest way to extract the time information from a digitized signal is to perform a digital Constant Fraction Discrimination (CFD) –Indeed, a simple threshold method introduces Time Walk which depends on the signal amplitude  to remove the time walk, threshold has to be set as a constant fraction of the signal amplitude  As seen above, this fraction should correspond to the highest Slope Over Noise ratio  Algorithm is simple: looking for the peak (with or without Spline), then going back down and performing an interpolation between samples around the threshold Extracting the time from the signal: CFD Fixed threshold t V Δt : time walk A1 Δt ~ 0 relative threshold : constant fraction of the peak! A2 A3 k x A1 k x A2 k x A3 V t

28. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 WaveCatcher V4 : 2 pulses with Tr = Tf = 1.6ns and FWHM = 5ns Distance between pulses : Δt ~ 0 Differential jitter = 4.61ps => sampling jitter ~ 3 ps 4.61ps rms Time measurement results : example with Δt ~ 0 All matrix positions are hit!

29. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Jitter vs Time distance between two pulses Source: randomly distributed set of two positive pulses Results are the same with negative pulses or distance between arches of a sine wave Jitter distribution after INL correction is almost flat => coherent with INL shape

30. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 NIM paper has been published Abstract: … There is a considerable interest to develop new time-of-flight detectors using, for example, micro- channel-plate photodetectors (MCP- PMTs). The question we pose in this paper is if new waveform digitizer ASICs, such as the WaveCatcher and TARGET, operating with a sampling rate of 2-3 GSa/s can compete with 1GHz BW CFD/TDC/ADC electronics... … Conclusion: … The fact that we found waveform digitizing electronics capable of measuring timing resolutions similar to that of the best commercially-available Ortec CDF/TAC/ADC electronics is, we believe, a very significant result. It will help to advance the TOF technique in future. [D. Breton et al. / Nuclear Instruments and Methods in Physics Research A 629 124 (2011) 123–132]

31. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Raw CFD measurement CFD with walk correction NIM paper: Fermilab beam test Jerry Va’Vra tested the adequation of 10µm MCPPMTs for time of flight measurements Conditions: ~40pe and low gain (2-3 10 4 ) Beam

32. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 NIM paper: SLAC laser test WaveCatcher Board Same conditions as for Fermilab test: 40pe and low gain (2-3 10 4 ) 100Hz Tektronix oscilloscope Χ² method: CFD method:

33. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 NIM paper: SLAC test summary There we are …

34. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 5 versions of the board between june 2008 and june 2010 V1 (3x) V2 (5x) V3 (10x) V4 (12x) V5 (20x) V1 to V4: many improvements and new features. V5: USB from 12 Mbits/s to 480 Mbits/s, external clock input

35. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 The USB Wave Catcher board V5 SAM Chip Dual 12-bit ADC 1.5 GHz BW amplifier. µ USB Reference clock: 200MHz => 3.2GS/s 2 analog inputs. DC Coupled. Trigger discriminators Trigger input Pulsers for reflectometry applications Board has to be USB powered => power consumption < 2.5W Trigger output Cyclone FPGA +5V Jack plug Clock input 480Mbits/s USB interface

36. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 2 DC-coupled 256-deep channels with 50-Ohm active input impedance ±1.25V dynamic Range, with full range 16-bit individual tunable offsets 2 individual pulse generators for test and reflectometry applications. On-board charge integration calculation. Integrated raw trigger rate counters Bandwidth > 500MHz Signal/noise ratio: 11.8 bits rms (noise = 650 µV RMS) Sampling Frequency: 400MS/s to 3.2GS/s Max consumption on +5V: 0.5A Absolute time precision in a channel (typical): without INL calibration: <20ps rms (3.2GS/s) after INL calibration <10ps rms (3.2GS/s) Relative time precision between channels: <5ps rms. Trigger source: software, external, internal, threshold on signals, 11 modes of trigger coincidence Acquisition rate (full events)Up to ~1 kHz over 2 full channels Acquisition rate (charge mode)Up to ~10 kHz over 2 channels Summary of the SAM-based WaveCatcher performances. SiPM multiple photon charge spectrum 1 5

37. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Goal is to precisely characterize the Antares opto- modules 1000000 triggers per measurement step 0.45% of triggers give a photoelectron (=> ~1.5% of statistical error) There are 289 measurement steps spaced by 1cm (3 degrees of aperture on the optical module) starting from its center Using the integrated charge mode, reading out the 289000000 events takes only 2h30. Example of use: PM characterization at APC 1 5

38. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 The WaveCatcher around the world We are active members of the international ps collaboration Our progress is presented there ~ twice a year. We started collaborating with the University of Chicago on the design of a very high frequency sampler (10 to 20 GS/s) in 130-nm technology. First prototypes have already been produced and a new one is awaited soon. There are many users of the WaveCatchers modules From the 50 modules produced, ~20 have been bought by different labs out of LAL and IRFU (CERN, Argonne Labs, Univ of Maryland, Stanford, Univ of Barcelona, APC, CENBG, IPHC, LPCG, …) Mostly used for test benches of fast detectors Their feedback is very useful to improve both the modules and the software

39. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Developments towards large scale implementations

40. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 We decided to set up a high precision TOF demonstrator for SuperB on the Cosmic Ray Telescope at SLAC (Stanford University). Therefore, we just built a synchronous sixteen channel acquisition system based on 8 two-channel WaveCatcher V5 boards Technical challenge: to keep the 10ps precision at the crate level Main requirements: 1.The system has to work with a common synchronous clock  There we take benefit of the external clock input of WaveCatcher V5 2. It is self-triggered but it also has to be synchronized with the rest of the CRT  Rate of cosmics is low thus computer time tagging of events is adequate (if all computers are finely synchronized) 3. Like WaveCatcher, data acquisition is based on 480Mbits/s USB. A 16-channel TOF on CRT at SLAC

41. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Experimental setup Patch panel 16 SMA connectors To amplifiers PM-side harness Trigger for the electronics crate (QTZ3) Faraday cage µ MCPPMT

42. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 42 Trig out CH0 CH1 Clk in Trig out Trig inTrig out CH0 CH1 Clk in Trig out Trig inTrig out CH0 CH1 Clk in Trig out Trig inTrig out CH0 CH1 Clk in Trig out Trig inTrig out CH0 CH1 Clk in Trig out Trig inTrig out CH0 CH1 Clk in Trig out Trig inTrig out CH0 CH1 Clk in Trig out Trig inTrig out CH0 CH1 Clk in Trig out Trig in USB Clk out Trig out Trig in Ext trig in 36dB Amp 36dB Amp 36dB Amp 36dB Amp 8 8 8 Ext trig out Clock and control board Patch panel 16 amplifiers DAQ PC From QTZ3 USB hub USB 8 8 USB WaveCatcher V5 Electronics setup

43. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 4-channel prototype Succesfully tested at CERN mid July 2010 on new high speed MRPCs

44. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Full crate

45. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Back of the crate

46. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 2 pulses Tr = Tf = 1.6ns FWHM = 5ns Δt = 0 ps CFD ratio = 0.23 Slope at CF ~ 400mV/ns Worst case: different channels on different boards Differential jitter = 5.78 ps rms Density is very homogeneous Characterization of multi-board system

47. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Time performance of multi-board system Mean differential jitter is of about 12ps rms which corresponds to 8.5 ps rms of time precision per pulse

48. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 The whole setup at SLAC

49. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 One cosmic event Recycled 6U crate Naked WaveCatchers mounted on 3U carrier boards

50. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Different typical signal shapes

51. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Single photoelectron time resolution between bars More than adequate for final physics goal of 50 ps with 5 to 10 photoelectrons Special thanks to L.Burmistrov

52. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 MCPPMT test bench at LAL

53. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Back view of the scanning setup

54. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Preliminary results We performed a first fast scan of the MCPPMT –Steps of 2 mm in X and Y => total of 900 steps –20 s per step to get ~500 events  total scan time of 5 hours (should be improved with software upgrade) –Example of an extracted 2-D efficiency plot for channel 6 –Charge sharing at the limit between pixels can be studied –Next steps: –timing studies –new Hamamatsu MCP

55. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Newest developments

56. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 SAMOS test ASIC SAMOS (submitted in 2009 in a cheap multiproject run) was purely intended to test various different options before their potential integration in other circuits Modified version of SAM (2 differential x 256 cells, matrix structure, pin compatible). MOS storage cells (8 x more compact than classic one => goal: increase the number of channels/chip) in the future chips One channel with MOS cells. One channel with classic ones. Low power operation ( expected gain > 5): No input amplifiers (lines of matrix short-circuited to input). Power pulsing: the readout part of the chip is powered only during readout. Other New features: Time interpolator added to measure trigger to clock time interval. Programmable postrig operation: The number of cells written after the trailing edge of the run signal is now programmable between 16 and 255 (was fixed to 32 in SAM). It was and still is a source of very interesting results for the following circuits –Some of the options (in green) were already kept for SAMLONG design –Others are still under study

57. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 The new SAMLONG ASIC SAM was a great demonstrator for precision time measurement. But in parallel there was a need for longer depth analog memories –A chip like SAM with 1024 cells and compatible with the WaveCatcher board was designed: SAMLONG. This chip also includes: –a time interpolator (“vernier”) for tagging the trigger arrival time (like in our former MATACQ chip). New input buffers (slew rate, power) New readout amplifiers (noise) Output multiplexor (single ADC) Internal programmable posttrig Target: same performances as SAM but less power (300mW => 200mW / 2ch) Everything we learnt from SAM for time precision was taken into account SAMLONG was submitted in April 2010 and received in September  It was mounted on a WaveCatcher V4 and worked immediatly !  SAMLONG_V2 has been submitted this week (part of dedicated run)  with a few little corrections and improvements

58. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 SAMLONG: a few plots

59. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 The USB Wave Catcher board V6 Native for SAMLONG and compatible with SAM. Also ready for the test of future chips. Redesign of the clock distribution to still reduce the jitter

60. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 SAMLONG vs SAM SAM better than SAMLONG after correction, but SAMLONG better than SAM before correction despite the factor 4 in length => improvement in the design of SAMLONG but it is more difficult to calibrate

61. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Summary of performances NAMESAMSAMLONGUnit Power Consumption300160-250mW Sampling Freq. Range0.4 to 3.20.4 to 3.2GS/sGS/s Analog Bandwidth (convoluted with board) 520375-460MHz Read Out time for a 16 cell event for full readout < 1.5 < 25 < 1.5 < 100 µs Fixed Pattern noise0.40.35mV rms Total noise (constant with frequency) 0.65 (0.5mV if FPN cancelled) 0.65 (0.55mV if FPN cancelled) mV rms Maximum signal (limited by ADC range) 2 (4 in diff) 2 (4 in diff) V Dynamic Range> 12 bits Crosstalk< 3 per mil Relative non linearity< 1 % Sampling Jitter raw INL corrected < 20 < 10 < 18 < 13 ps rms

62. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 From a crate to a 16-channel board 8 x 75 = 600 mm ! 145 mm There is an increasing demand in high-scale/ very high speed/high precision boards. This kind of boards could also be used as high precision TDC Power and cost have to remain reasonable => < 20W => a few k€

63. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Under design: a 16-channel WaveCatcher Based on the very encouraging results of the 16-channel crate, we started the design of a 16-channel WaveCatcher board This board will be compatible with both SAM (256 cells/ch) and SAMLONG (1024 cells/ch) –The board can be synchronized externally => possibility to scale the system up to 320 channels in a crate The first prototype will be available in September 2011 SAMLONG Chip 1024 pts - 3.2 GS/s 2 Channels Dual 12 bits ADC SAMLONG Chip 1024 pts - 3.2 GS/s 2 Channels Dual 12 bits ADC 4 Analog Input Trigger In/out SAMLONG Chip 1024 pts - 3.2 GS/s 2 Channels Dual 12 bits ADC SAMLONG Chip 1024 pts - 3.2 GS/s 2 Channels Dual 12 bits ADC FPGA 4 Analog Input Trigger In/out FPGA  VME Format  USB 480 Mbits/s  Optical fiber output

64. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Board features (not exhaustive)  Possibility to add an individual DC offset on each signal  Possibility to chain channels by groups of 2  2 individual trigger discriminators on each channel  External and internal trigger + numerous modes of triggering on coïncidence (11 possibilities including two pulses on the same channel => useful for afterpulse studies  Embedded digital CFD for time measurement  Embedded signal amplitude extraction  Embedded charge mode (integration starts on threshold or at a fixed location) => high rates (~ 3.5 kEvents/s)  2 extra memory channels for digital signals  One pulse generator on each input  External clock input for multi-board applications  Embedded USB and Ethernet interfaces

65. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Low Threshold + - + - High Threshold SAMLONG Ch0 FPGA Controller ½ Front End FPGA (TimeStamp,Q,A) L1 primitives CONTROLLERBOARDCONTROLLERBOARD 12-bit ADC Low Threshold + - + - High Threshold Ch1 L1 Trigger Ch0 Ch1 Run, read clk Event data Board Schematic Principle x 8 Optional: if more than 16 channels USB

66. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Status of PCB design (by P.Rusquart, LAL) As of today 4-channel blocks can be used as mezzanine on other boards

67. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 Towards a ps TDC … In order to build a real TDC targetting the ps level, adding an analog memory to a usual DLL TDC permits relieving the walk constraint on the discriminator and improving the time precision by an order of magnitude (our patent: FR0954226) Here the Delay Line is servo-controlled and can be as short as the signal to measure => very good time resolution can be envisaged Critical path for time measurement Solution with companion FPGA Fully integrated solution

68. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 We have now in hand all the information we need to design new analog memory ASICs, boards and systems targeting one or more of: –A lower power consumption –A higher sampling frequency –A higher signal bandwidth –A greater sampling depth –A higher density –A higher time precision –A higher modularity between the number of channels and their length These circuits which should be submitted in 2011 and later will be increasingly used in many fields of high energy physics, astrophysics, and in the characterization of very fast captors (like ultra-fast PMTs, SiPMs, silicon detectors, …). A PHD student will participate in these designs from Sept 2011 on. –AMS 0.18µm technology should be used (at last …) => good compromise for mixed signal designs Future

69. D. Breton, E. Delagnes, J. Maalmi – Journée R&D P2I – Orsay – Juin 2011 All of this recent costly but fruitful innovation was permitted thanks the funding of P2I of this collaborative work, which was of the highest importance for us. It is very difficult to get money for generic R&D, and P2I thus was a wonderful support to this end. Therefore we intend to apply again to any future equivalent project call in order to be able to pursue this successful design story. Conclusion