1. © 2007 IBM Corporation Power6 Presentation Power of P6 Anita Devadason June 11 th, 2007

2. Power6 Presentation © 2007 IBM Corporation Agenda  Overview of Processor Chip Development –High Level Design –Verification  Overview of Server Development  Interaction between Operating System and Hardware  Power6 Chip Layout  What’s New in Power6 Chip  What’s New in Power6 System –Fabric Connections –Monitors –LPAR/micro-partition  Comparison of Power5 System and Power6 System –Chip Layout –Characteristics –System Topology –I/O buses  IO Bus Speeds  Top Five Reasons to Buy Power6 System

3. Power6 Presentation © 2007 IBM Corporation Overview of Processor Chip Development DesignVerificationConcept Release to Manufacturing Fabrication Process Virtual Bring-Up (VBU) WaferLabChip

4. Power6 Presentation © 2007 IBM Corporation High Level Design Design Core Nest Unit 1 Unit 2 Unit N Unit 1 Unit 2 Unit N Ex: IFU Ex: IDU Ex: LSU Ex: NCU Ex: L2 Ex: L3

5. Power6 Presentation © 2007 IBM Corporation Verification (Test Design on Pre-Silicon) Chip 1 Core Nest Unit 1Unit 2Unit NUnit 1Unit 2Unit N Chip N System MicroprocessorI/O & Memory

6. Power6 Presentation © 2007 IBM Corporation Overview of Server Development Virtual Power-ON (VPO) Integration Firmware Chip on CardCard Design GA AIX Lab Note: Various intermediate testing is done at each levels which is not mentioned here

7. Power6 Presentation © 2007 IBM Corporation Interaction between Operating System and Hardware OS (AIX) Hypervisor (pHyp) Firmware (pFW) Hardware (HW)

8. Power6 Presentation © 2007 IBM Corporation Power6 Chip Layout

9. Power6 Presentation © 2007 IBM Corporation What’s New in Power6 Chip  New Technology (11s)  Supports both Little and Big Endian  Supports page sizes of 4K, 64K, 16M, and 16G  New decimal floating point operations for performance and accuracy  Enhanced data pre-fetching for performance  VMX (Vector Multimedia eXtension) for accelerated graphics  Error detection and recovery mechanisms similar to system z  Enhanced power and thermal control including power savings  Local/Global Address Broadcast in system bus for better performance  Supports both GX+ and GX++ for legacy and new I/O protocols –GX+ uses RIOG, Federation, or Infiniband (2.5 GHz) –GX++ uses Infiniband Gen2 DDR (5.0 GHz)  Multiple shared processor pools (target 4Q07 with AIX 5.4) so we can group multiple Oracle applications into one shared pool. At the moment, we have one shared processor pool.  Shared memory pools will be available (target 4Q07 with AIX 5.4)

10. Power6 Presentation © 2007 IBM Corporation What’s New in Power6 System – Fabric

11. Power6 Presentation © 2007 IBM Corporation What’s New in Power6 System - Monitors

12. Power6 Presentation © 2007 IBM Corporation What’s New in Power6 System – LPAR DLPAR – Dynamic Logical Partitions which means partitions can switch on the fly (available in P5 also) Source Partition  Null Partition  Target Partiton Micro-partition – minimum 1/10 th of a core Active micro-partition can move between servers with no loss of service

13. Power6 Presentation © 2007 IBM Corporation Comparison - Characteristics Power5Power6 TechnologyCMOS9S2CMOS11S Die Size386 mm 2 341 mm 2 Power180WTBD Frequency1.5-2.3 GHz4-5 GHz PackagingChips on Module (DCM, MCM, QCM) Chips on Card L2 Cache(1) 2 MB(2) 4 MB L3 Controller/Cache36 MB32 MB Memory Controller12 # of LPARS/system2541024? # of cores/LPAR64512 LPIDR7 bits10 bits

14. Power6 Presentation © 2007 IBM Corporation Comparison – Chip Layout Power5 Power6

15. Power6 Presentation © 2007 IBM Corporation Comparision – System Topology

16. Power6 Presentation © 2007 IBM Corporation Comparison – I/O Buses P5 Chip Bridge Chip GX Bus RIO Bus IO Devices Bridge Chip PCI Bus P5 Chip Bridge Chip GX+ Bus RIOG or Federation Bus IO Devices PCIX Bus P6 Chip Bridge Chip GX+ Bus RIOG or Federation or Infiniband Bus IO Devices Bridge Chip Bridge Chip PCIX or PCIX Gen2 DDR Bus P6 Chip Bridge Chip GX++ Bus Infiniband Gen2 DDR Bus IO Devices PCIX Gen2 DDR or PCIE Bus Bridge Chip

17. Power6 Presentation © 2007 IBM Corporation I/O Bus Speeds Bus NameData RateFrequency RIO (aka RIO1)500 MB/s250 MHz RIOG (aka RIO2)1 GB/s500 MHz Infiniband Gen1 *250 MB/s each way2.5 GHz Infiniband Gen2 DDR * 500 MB/s each way5.0 GHz PCI500 MB/s66 MHz PCIX Gen11 GB/s133 MHz PCIX Gen2 DDR2 GB/s266 MHz PCIE Gen1 *250 MB/s each way2.5 GHz PCIE Gen2 DDR *500 MB/s each way5.0 GHz * - indicates point to point protocol

18. Power6 Presentation © 2007 IBM Corporation Top Five Reasons to Buy Power6 System 1.Fastest server in the industry to date with great price/performance. 2.Better RAS (Reliability, Accessibility, and Serviceability) capabilities. Error detection and recovery mechanisms similar to system z (p6 core shares some of the same building blocks as z6 core). 3.More flexibilities and options to consolidate IT data center. 4.Energy efficient so your data center stays or becomes “green.” 5.Multiple shared processor pools to reduce ISV licensing prices.

19. Power6 Presentation © 2007 IBM Corporation Disclaimer Information in this presentation is from STG development and this does not indicate the future direction of how products would ship since products could change or be withdrawn without notice. This information was put together to educate people within IBM.