1. A Front End ASIC for the read out of the PMT in the KM3NeT Detector NIKHEF, (National Institute of Subatomic Physics) Amsterdam, The Netherlands 21-09-20101D. Gajanana TWEPP 2010 Topical Workshop on Electronics for Particle Physics 20-24 September 2010 Aachen, Germany

2. Introduction to the KM3NeT Experiment. KM3NeT Detector Concept. Read out electronics. Specifications of the ASIC. The Circuit. Test Results. Conclusions & Future. Contents D. Gajanana TWEPP 2010221-09-2010

3. Neutrinos are unique messengers from the most violent, highest-energy processes in our Galaxy and far beyond. Neutrino astronomy is experimentally highly demanding, requiring vast volumes of target material, such as water or ice & dark environment. KM3NeT Experiment D. Gajanana TWEPP 2010321-09-2010 Toulon (France) Pylos (Greece) Capo Passero (Italy)

4. The detection of high ‐ energy muon neutrinos exploits the emission of Cherenkov light by the muon and other charged secondary particles produced in a neutrino interaction. Photo-Multiplier-Tubes (PMTs) housed in glass spheres (optical modules), are deployed in the deep sea. KM3NeT Detector concept D. Gajanana TWEPP 2010421-09-2010 320m

5. Read-Out Electronics D. Gajanana TWEPP 2010521-09-2010 ASIC P. Timmer’s talk 31 ASICs per Optical Module

6. Time resolution : 2ns (Photon arrival time accuracy) Time-over-Threshold : 1pe → 25ns (800 000 e - )..10pe → 350ns (8000000e - ) Number of channels : several hundred thousands. LVDS signaling. I 2 C slow control. Comparator threshold adjustment: 0…375 000 e - → V in com = ±200mV Resolution : 8bits (bin size=1500 e - / 1.2mV) Reference voltages for High Voltage circuit: 2.0V …2.8V (resolution 8bits) → High Voltage: -700V …-1500V Power consumption : ~ 20mW Technology: 0.35μm CMOS (AustriaMicroSystems) Immunity to dirty Power supplies Immunity to voltage breakdowns originated in the PMT Specifications of the ASIC D. Gajanana TWEPP 2010621-09-2010

7. Introduction to the KM3NeT Experiment. KM3NeT Detector Concept. Read out electronics. Specifications of the ASIC. The Circuit. Test Results. Conclusions & Future. Contents D. Gajanana TWEPP 2010721-09-2010

8. Analog Part D. Gajanana TWEPP 2010821-09-2010 Virtuoso Schematic Entry Schematic Entry ADE / Spectre Simulation Virtuoso Layout Editor Layout Bandgap 1.2V Bias Block + Threshold setting DAC for Comparator HV setting DAC + Opamp for HV feedback PreampComparatorBuffersLVDS DAC settings from I 2 C From PMT LVDS DAC output Opamp output Opamp input (HV circuit on PCB) Prototyped before

9. Preamplifier D. Gajanana TWEPP 2010921-09-2010 Two-stage charge preamplifier with RC feedback. Time-to-Threshold 2 photons 1 photon IN REF. Preamp 1V OUT 0.5 mA 125 μA 15kΩ 300 fF Time-over-Threshold

10. Comparator D. Gajanana TWEPP 20101021-09-2010 Single Stage comparator. IN OUT Threshold 0.8 – 1.2V 375 μA

11. LVDS Driver D. Gajanana TWEPP 20101121-09-2010 Conventional LVDS driver, single stage CMFB circuit. 3.5mA * 100Ω = 350mV differential signal. Pbias Nbias X X IN+IN- OUT- OUT+ CM REF. 1.2V 0.5 mA 3.5 mA 100k

12. VHDL, VERILOG Text Editor, EASE, EALE Design Entry ModelSim Simvision Simulation Synopsys Synthesis ModelSim Simvision Simulation Synopsys Scan Chain Insertion SOC Encounter Physical Layout ModelSim Simvision Simulation Digital Part D. Gajanana TWEPP 20101221-09-2010 Clock Generator ~ 10MHz POR PROM 20Bits I2C Decoder + PROM Control Logic I 2 C BUS Burn Enable Clk Enable To DACs Scan Chain Analog Chain Test HV on-off Verilog Netlist Data Control Verilog Netlist + SDF files

13. Digital Simulations - Example D. Gajanana TWEPP 20101321-09-2010 I2CI2C PROM DAC + HV + Control & Test Post Layout simulations with SDF files (Digital Part only). Tools Used : Modelsim, ncSim suite, Synopsys.

14. Analog Bondpad Modifications D. Gajanana TWEPP 20101421-09-2010 Previous pad Present pad Possible Solution Vdd I/O Gnd Internal Circuitry Power Clamp Vdd I/O Gnd Internal Circuitry Power Clamp Time jitter on the falling edge Power supply ripples = ±40mV Unavoidable – From HV Supply on PCB Problem ~0.23pF

15. Layout & Integration D. Gajanana TWEPP 20101521-09-2010 Band gap Bias Block HV Control Block Prea mp Compa rator + Buffers LVDS Clock Genrtr POR I2C Decoder + PROM Control PROM 1.8 mm Digital Part Analog Part Pads, Scribe lines Final Layout

16. Mixed-Signal Simulation Results D. Gajanana TWEPP 20101621-09-2010 Post Layout including Bondpads simulations. Tools Used : AMS environment (Ultrasim/spectre and ncSim suite). Final Simulation Results Pads, Scribe lines Analog Part Digital Part I2CI2C Comparator DAC HV DAC LVDS

17. Preliminary tests only. 3 samples packaged and tested. I 2 C communication successful. DAC settings changeable. Analog chain functional. Test Setup D. Gajanana TWEPP 20101721-09-2010

18. Test Results D. Gajanana TWEPP 20101821-09-2010 Time-to- Threshold 2 photons 1 photon Time walk=3 ns

19. Test Results D. Gajanana TWEPP 20101921-09-2010 Time-over-Threshold 2 photons 1 photon

20. An ASIC to read out the PMT was successfully designed, simulated, fabricated and tested. Preliminary “Test results” are satisfactory & in line with simulation results and future functionality is being tested. More intensive tests need to be performed on the ASIC. We aim an engineering run during Q1 of 2011, allowing for a production ramp-up in Q1 of 2012. Conclusions & Future D. Gajanana TWEPP 20102021-09-2010

21. KM3NeT project team, V. Gromov, Eric Heine, Ruud Kluit, John Hug, Jan-Willem Schmelling, P. Jansweijer, V. Zivkovic, P. Timmer, Joop Rovekamp, ET colleagues at NIKHEF. Thank You D. Gajanana TWEPP 20102121-09-2010 References www.km3net.org/CDR/CDR-KM3NeT.pdf www.km3net.org/TDR/Prelim-TDR-KM3NeT.pdf Prof. Sansen “Analog Design Essentials” Springer, 2006. Chang ZY, Sansen W. “Low-noise wide band amplifiers in Bipolar and CMOS technologies” Springer, 1996. Tajalli et. al. “A Slew Controlled LVDS Output Driver Circuit in 0.18 μm CMOS Technology”, JSSC, Feb. 2009. www.national.com/LVDS J.Vandenbussche et. al. “A fully integrated Low-Power CMOS Particle Detector Front- End for space applications”, IEEE Trans. on Nuclear Science, Aug. 1998.

22. D. Gajanana TWEPP 20102221-09-2010 Effect of the ripple on the power supply bus Ripples on the Vdd bus : ± 40mV Output LVDS signals time jitter on the falling edge PSRR is an issue

23. ESD Protection D. Gajanana TWEPP 20102321-09-2010

24. Bandgap Circuit ◦Supply = 3.3V, Supply current ≈ 50μA, Power ≈ 150μW. ◦Vref = 1.21V, TK = 40ppm, Startup = 20μs, Isource = 275μA, Isink = 32μA. DAC ◦Two Resistor divider based architecture. ◦Supply = 3.3V, Supply current ≈ 100μA, Power ≈ 100μW (Ref = 1V). ◦Rout ≈ 21kΩ, INL,DNL,Vos ≈ 1/4 *LSB. Opamp ◦Miller Compensated, 2 Stage opamp. ◦Supply = 3.3V, Supply current ≈ 0.3mA, Power ≈ 1mW. ◦GBW = 2.5MHz, Open loop gain ≈ 100dB, Isource ≈ 0.25mA. Analog Part D. Gajanana TWEPP 20102422-09-2010

25. D. Gajanana TWEPP 20102521-09-2010 Time-to- Threshold, nsec Number of photons (1photon = 10 6 e - ) Low gain version High gain version Vdd=3V, 3.3V, 3.6V Number of photons (1photon = 10 6 e - ) Time-to- Threshold, nsec Time-to- Threshold 2 photons 1 photon Time-to- Threshold 2 photons 1 photon Time walk=2.7ns Time walk=1.4ns Conclusion: the low gain version has larger time walk (improves if the threshold is lower) Arrival time (Time-to-Threshold time measurements)

26. D. Gajanana TWEPP 20102621-09-2010 Time- over- Threshold, nsec Number of photons (1photon = 10 6 e - ) Low gain version High gain version Vdd=3V, 3.3V, 3.6V Number of photons (1photon = 10 6 e - ) Time- over- Threshold, nsec Time-over-Threshold 2 photons 1 photon Time-to- Threshold 2 photons 1 photon Vdd=3V, 3.3V, 3.6V Conclusion: the low gain version is less sensitive to Vdd instability Charge deposit (Time-over-Threshold measurements)