1. wei-chih A Low-Voltage Low-Power Sigma-Delta Modulator for Broadband Analog-to-Digital Conversion IEEE Journal Of Solid-state Circuits, Vol. 40, No. 9, September 2005 Kiyoung Nam, Student Member, IEEE, Sang-min Lee, Student Member, IEEE, David K. Su, Senior Member, Ieee,and Bruce A. Wooley, Fellow, IEEE Wei-Chih

2. 1 wei-chih Outline Abstract Introduction Architecture Power minimization Implementation Measurements Conclusion

3. 2 wei-chih Abstract A cascade(2-2) of sigma-delta modulator with employ a feedforward architecture and date weighted averaging (shifter). Dynamic range of 96 dB for a 1.25-MHz signal bandwidth. The implement in 0.25μm CMOS technology  Analog power dissipation is 44mW.  Digital power dissipation is 43mW.

4. 3 wei-chih Introduction Considerations of cost and performance.  Cost: Reduction in supply voltage. Advanced CMOS technologies problematic. Systematic means of power minimizing.  Noise-and-settling constrained power minimization (NSCPM).  Performance: Limited of supply voltage available.  Circuits limited by thermal noise, noise floor.  Leads to an increase in power dissipation. To achieve the targeted performance objectives.  Architectural to maximizing the input signal range in ΣΔ modulator.

5. 4 wei-chih Architecture Architecture (cont.) Conventional first-order ΣΔ modulator. First-order reduced integrator swing range (RISR) ΣΔ modulator.

6. 5 wei-chih Architecture Architecture (cont.) A large signal at the integrator output causes three problems. (Conventional)  Distortion Results from the clipping of integrator output.  To maintain a given dynamic range. (Power ↑ )  Harmonics Associated variation of op amp dc gain.  Gain enhancement. (Power ↑ )  OP architectural. (Same gain and bandwidth) Single-stage. Two-stage. (Power ↑ )

7. 6 wei-chih RISR ΣΔ modulator architecture.  Advantages The signal ranges required for and can be greatly reduced by. Smaller avoids op amp slewing. (Power ↓ ) Smaller is favorable at low supply voltages.  Single-stage OP. (Power ↓ ) is now decoupled from the input.  A large full-scale input range can be used. (Power ↓ ) The op amp dc gain and settling time constant requirements are greatly relaxed. Architecture Architecture (cont.)

8. 7 wei-chih Architecture Architecture (cont.) RISR ΣΔ modulator architecture.  Quantization error Large swings in are not problematic because this signal immediately precedes the quantizer. Second-order reduced integrator swing range (RISR) ΣΔ modulator.

9. 8 wei-chih Architecture Architecture (cont.) Maximum magnitudes of integrator inputs and outputs versus input level for different second-order ΣΔ modulator topologies. 1st input 1st output 2nd input 2nd output

10. 9 wei-chih Architecture Architecture (cont.) Maximum magnitudes of integrator inputs and outputs versus OSR for different second-order ΣΔ modulator topologies. 1st input 1st output 2nd input 2nd output

11. 10 wei-chih Architecture Architecture (cont.) RISR ΣΔ modulator architecture.  Disadvantages The timing overhead is greater.  Because the delay from the feedback. Increased power dissipation in the comparators. (Quantizer)  Fast amplification and regeneration.  Small input-referred offset.  This power penalty is small in comparison with the power saved in the op amps used to implement the integrators.

12. 11 wei-chih Architecture The RISR architecture can be expanded.  Order = L.  Bits = N.(N ≥ L)  = minimize. To avoid the op amp slewing.  = Maximize. To minimize the power dissipation.

13. 12 wei-chih Power minimization Power minimization (cont.) The procedure is described by the flow graph.  MIDAS Op amp dc gains. Settling time constants.

14. 13 wei-chih Power minimization Power minimization (cont.) Integrator Settling. The input-referred thermal noise power of a switched-capacitor integrator.

15. 14 wei-chih Power minimization Power minimization (cont.) NSCPM algorithm. NSCPM Minimization of the sum of the two integrator transconductance (17) is the objective or cost function of the NSCPM procedure.

16. 15 wei-chih Power minimization Power minimization (cont.) NSCPM results NSCPM  _ 12.8pF 0.598 30

17. 16 wei-chih Power minimization Power minimization (cont.) First integrator noise distribution between the switch noise and the op amp noise versus. Circuit parameters: =54mS,=12.8pF,=30 Ω. =5.8mS,=2.8pF,=71 Ω. 12.8pF

18. 17 wei-chih Power minimization Final architecture.

19. 18 wei-chih Implementation Implementation (cont.) First stage. Op amp for the first integrator. The final op amp at least 57 db of gain across all process corners. Four integrators in the two-stage cascade are scaled in succession by 1, 1/4, 1/16, and 1/32.

20. 19 wei-chih Implementation Comparator for the first and second quantizers. Signal: : store the preamp offset, cancel offset.

21. 20 wei-chih DR of 96 dB was achieved with a peak SNDR of 89 dB at 366-kHz BW. SFDR of 97 dB with 109-kHz BW Measurements Measurements (cont.)

22. 21 wei-chih Measurements Summary of measured performance

23. 22 wei-chih Conclusion The use of a (RISR) modulator architecture  Minimizes the signal ranges required at the inputs and outputs of the forward-path integrators.  Single-stage op amp implementation of these integrators, even at low voltage. The power minimization procedure (NSCPM) has the added advantage of providing quantitative information about the trade-off between power, linearity, and area.